►Nmptl | |
►Nirq | |
Cspi | |
Cspi< 1 > | |
Cspi< 2 > | |
Cusart | |
Cusart< 1 > | |
Cusart< 2 > | |
Cusart< 3 > | |
►Cadc | |
Cdata_align | Data alignment |
Cdual_mode | Dual mode selection |
Cexternal_trigger_conversion | External event select for regular group |
►CADC | Analog-to-digital converter (ADC) |
CCR1 | Control register 1 |
CCR2 | Control register 2 |
CDR | Regular data register |
CHTR | Watchdog higher threshold register |
CJDR | Injected data register x |
CJOFR | Injected channel data offset register x |
CJSQR | Injected sequence register |
CLTR | Watchdog lower threshold register |
CSMPR1 | Sample time register 1 |
CSMPR2 | Sample time register 2 |
CSMPRx | Sample time register: provides SMPR1 or SMPR2, depending on channel |
CSQR1 | Regular sequence register 1 |
CSQR2 | Regular sequence register 2 |
CSQR3 | Regular sequence register 3 |
CSQRx | Regular sequence register: provides SQR1, SQR2 or SQR3, depending on channel |
CSR | Status register |
Carm_cortex_vector_table [external] | |
Cbitband_periph [external] | |
Ccore_base [external] | |
Ccore_exception [external] | |
Ccounted_ring_buffer [external] | |
Ccycle_counter [external] | |
CDEBUG [external] | |
Cdwt [external] | |
CDWT [external] | |
Cfifo [external] | |
►CFLASH | Embedded Flash memory (FLASH) |
CACR | Flash access control register |
CAR | Flash address register |
CCR | Control register |
CKEYR | Flash key register |
COBR | Option byte register |
COPTKEYR | Flash option key register |
CSR | Status register |
CWRPR | Write protection register |
►Cflash | |
Clatency | |
►CGPIO | General-purpose and alternate-function I/Os (GPIOs and AFIOs) |
CCRx | GPIO port configuration register: returns CRL or CRH type dependent on pin_no |
►Cgpio | |
Cinput_type | |
Cmode | |
Coutput_type | |
Cgpio_analog_io_base [external] | |
Cgpio_input | |
Cgpio_input_base [external] | |
Cgpio_led | |
Cgpio_led_base [external] | |
Cgpio_output | |
Cgpio_output_base [external] | |
Cirq_base [external] | |
Cirq_channel [external] | |
Cirq_handler [external] | |
Cirq_handler_base [external] | |
CMPU [external] | |
CNVIC [external] | |
►CPWR | Power control |
►CCR | Power control register (PWR_CR) |
►CPLS | PVD Level Selection |
Cvoltage_threshold | |
CCSR | Power control register (PWR_CR) |
Cpwr | |
►CRCC | Reset and clock control |
CAHBENR | AHB Peripheral Clock enable register (RCC_AHBENR) |
CAHBRSTR | AHB peripheral clock reset register (RCC_AHBRSTR) (only available on connectivity line devices!) |
CAPB1ENR | APB1 peripheral clock enable register (RCC_APB1ENR) |
CAPB1RSTR | APB1 peripheral reset register (RCC_APB1RSTR) |
CAPB2ENR | APB2 peripheral clock enable register (RCC_APB2ENR) |
CAPB2RSTR | APB2 peripheral reset register (RCC_APB2RSTR) |
►CBDCR | Backup domain control register (RCC_BDCR) |
CRTCSEL | RTC clock source selection |
►CCFGR | Clock configuration register (RCC_CFGR) |
CADCPRE | ADC prescaler |
CHPRE | AHB prescaler |
CMCO | Microcontroller Clock Output |
COTGFSPRE | USB OTG FS prescaler (only available on connectivity line devices!) |
CPLLMUL | PLL Multiplication Factor |
CPLLSRC | PLL entry clock source |
CPLLXTPRE | |
CPPRE1 | APB low speed prescaler (APB1) |
CPPRE2 | APB high speed prescaler (APB2) |
CSW | System clock switch |
CSWS | System clock switch status |
CUSBPRE | USB prescaler (not available on connectivity line devices!) |
►CCFGR2 | Clock configuration register2 (RCC_CFGR2) (only available on connectivity line devices!) |
CI2S2SRC | I2S2 clock source |
CI2S3SRC | I2S3 clock source |
CPREDIV1SRC | PREDIV1 entry clock source |
CCIR | Clock interrupt register (RCC_CIR) |
CCR | Clock control register |
CCSR | Control/status register (RCC_CSR) |
►Crcc | |
Crtc_clock_source | |
Crcc_adc_clock_resources | |
Crcc_adc_clock_resources< 1 > | |
Crcc_adc_clock_resources< 2 > | |
Crcc_gpio_clock_resources | |
Crcc_gpio_clock_resources< 'A'> | |
Crcc_gpio_clock_resources< 'B'> | |
Crcc_gpio_clock_resources< 'C'> | |
Crcc_gpio_clock_resources< 'D'> | |
Crcc_gpio_clock_resources< 'E'> | |
Crcc_spi_clock_resources | |
Crcc_spi_clock_resources< 1 > | |
Crcc_spi_clock_resources< 2 > | |
Crcc_spi_clock_resources< 3 > | |
Crcc_usart_clock_resources | |
Crcc_usart_clock_resources< 1 > | |
Crcc_usart_clock_resources< 2 > | |
Crcc_usart_clock_resources< 3 > | |
Creg [external] | |
Creg_access [external] | |
Cregbits [external] | |
Creglist [external] | |
Cregmask [external] | |
Cregval [external] | |
Cring_buffer [external] | |
►CRTC | Real time clock |
CALRH | RTC Alarm register high |
CALRL | RTC Alarm register low |
CCNTH | RTC Counter register high |
CCNTL | RTC Counter register low |
CCRH | RTC Control register high |
CCRL | RTC Control register low |
CDIVH | RTC Prescaler divider register high |
CDIVL | RTC Prescaler divider register low |
CPRLH | RTC Prescaler load register high |
CPRLL | RTC Prescaler load register low |
Crtc | |
Csane_typelist [external] | |
CSCB [external] | |
CSPI | |
Cspi | |
CSPI< 1 > | |
CSPI< 2 > | |
CSPI< 3 > | |
CSPI_Common [external] | |
CSPI_Common_Ext [external] | |
Cspi_stm32_common [external] | |
Csystem_clock_hse | |
Csystem_clock_hse< mhz(24), mhz(8) > | |
Csystem_clock_hse< mhz(36), mhz(8) > | |
Csystem_clock_hse< mhz(48), mhz(8) > | |
Csystem_clock_hse< mhz(56), mhz(8) > | |
Csystem_clock_hse< mhz(72), mhz(8) > | |
Csystem_clock_hse_impl | |
Csystick [external] | |
Csystick_clock [external] | |
CTIM | |
CTIM< 1 > | |
CTIM< 10 > | |
CTIM< 11 > | |
CTIM< 12 > | |
CTIM< 13 > | |
CTIM< 14 > | |
CTIM< 2 > | |
CTIM< 3 > | |
CTIM< 4 > | |
CTIM< 5 > | |
CTIM< 6 > | |
CTIM< 7 > | |
CTIM< 8 > | |
CTIM< 9 > | |
CTIM_common [external] | |
Ctypelist_element [external] | |
Ctypelist_unique_element [external] | |
CUSART | |
Cusart | |
CUSART< 1 > | |
CUSART< 2 > | |
CUSART< 3 > | |
CUSART_common [external] | |
CUSART_common_ext [external] | |
Cusart_irq_stream [external] | |
Cusart_stm32_common [external] | |
Cvector_table [external] | |
Cirq_base< irqn > [external] | |
Creg_access< Tp, addr, permission, _reset_value > [external] | |
Cregbits< reg_type, offset+bit_no, 1 > [external] | |
Cregmask< reg_type,((1ul<< width) - 1)<< offset,((1ul<< width) - 1)<< offset > [external] | |
Cregmask< Tp,((1ul<< width) - 1)<< offset,((1ul<< width) - 1)<< offset > [external] | |
Cregmask< Tp::reg_type, Tp::value_from(_value), Tp::clear_mask > [external] | |
CSPI_Common< base_addr > [external] | |
Ctypelist_unique_element< irq_handler_base > [external] | |