Reset and clock control.
#include <rcc.hpp>
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struct | AHBENR |
| AHB Peripheral Clock enable register (RCC_AHBENR) More...
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struct | AHBRSTR |
| AHB peripheral clock reset register (RCC_AHBRSTR) (only available on connectivity line devices!) More...
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struct | APB1ENR |
| APB1 peripheral clock enable register (RCC_APB1ENR) More...
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struct | APB1RSTR |
| APB1 peripheral reset register (RCC_APB1RSTR) More...
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struct | APB2ENR |
| APB2 peripheral clock enable register (RCC_APB2ENR) More...
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struct | APB2RSTR |
| APB2 peripheral reset register (RCC_APB2RSTR) More...
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struct | BDCR |
| Backup domain control register (RCC_BDCR) More...
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struct | CFGR |
| Clock configuration register (RCC_CFGR) More...
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struct | CFGR2 |
| Clock configuration register2 (RCC_CFGR2) (only available on connectivity line devices!) More...
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struct | CIR |
| Clock interrupt register (RCC_CIR) More...
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struct | CR |
| Clock control register. More...
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struct | CSR |
| Control/status register (RCC_CSR) More...
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◆ base_addr
constexpr reg_addr_t mptl::RCC::base_addr = 0x40021000 |
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static |
The documentation for this struct was generated from the following file:
- arch/arm/cortex/stm32/f1/include/arch/reg/rcc.hpp