OpenMPTL - STM32F10X
C++ Microprocessor Template Library
rcc.hpp
Go to the documentation of this file.
1 /*
2  * OpenMPTL - C++ Microprocessor Template Library
3  *
4  * Copyright (C) 2012-2017 Axel Burri <axel@tty0.ch>
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License as published by
8  * the Free Software Foundation; either version 3 of the License, or
9  * (at your option) any later version.
10  *
11  * This program is distributed in the hope that it will be useful,
12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14  * GNU General Public License for more details.
15  *
16  * You should have received a copy of the GNU General Public License
17  * along with this program. If not, see <http://www.gnu.org/licenses/>.
18  *
19  */
20 
21 /*
22  * This program contains derivative representations of CMSIS System
23  * View Description (SVD) files, and is subject to the "End User
24  * License Agreement for STMicroelectronics" (see "STM_License.html"
25  * in the containing directory).
26  */
27 
28 #ifndef ARCH_REG_RCC_HPP_INCLUDED
29 #define ARCH_REG_RCC_HPP_INCLUDED
30 
31 #include <register.hpp>
32 
33 namespace mptl {
34 
35 /**
36  * Reset and clock control
37  */
38 struct RCC
39 {
40  static constexpr reg_addr_t base_addr = 0x40021000;
41 
42  /**
43  * Clock control register
44  */
45  struct CR
46  : public reg< uint32_t, base_addr + 0x0, rw, 0x00000083 >
47  {
48  using HSION = regbits< type, 0, 1 >; /**< Internal High Speed clock enable */
49  using HSIRDY = regbits< type, 1, 1 >; /**< Internal High Speed clock ready flag */
50  using HSITRIM = regbits< type, 3, 5 >; /**< Internal High Speed clock trimming */
51  using HSICAL = regbits< type, 8, 8 >; /**< Internal High Speed clock Calibration */
52  using HSEON = regbits< type, 16, 1 >; /**< External High Speed clock enable */
53  using HSERDY = regbits< type, 17, 1 >; /**< External High Speed clock ready flag */
54  using HSEBYP = regbits< type, 18, 1 >; /**< External High Speed clock Bypass */
55  using CSSON = regbits< type, 19, 1 >; /**< Clock Security System enable */
56  using PLLON = regbits< type, 24, 1 >; /**< PLL enable */
57  using PLLRDY = regbits< type, 25, 1 >; /**< PLL clock ready flag */
58  using PLL2ON = regbits< type, 26, 1 >; /**< PLL2 enable (only available on connectivity line devices!) */
59  using PLL2RDY = regbits< type, 27, 1 >; /**< PLL2 clock ready flag (only available on connectivity line devices!) */
60  using PLL3ON = regbits< type, 28, 1 >; /**< PLL3 enable (only available on connectivity line devices!) */
61  using PLL3RDY = regbits< type, 29, 1 >; /**< PLL3 clock ready flag (only available on connectivity line devices!) */
62  };
63 
64  /**
65  * Clock configuration register (RCC_CFGR)
66  */
67  struct CFGR
68  : public reg< uint32_t, base_addr + 0x4, rw, 0x00000000 >
69  {
70  /** System clock switch */
71  struct SW
72  : public regbits< type, 0, 2 >
73  {
74  using HSI = regval< regbits_type, 0x0 >; /**< 00: HSI selected as system clock */
75  using HSE = regval< regbits_type, 0x1 >; /**< 01: HSE selected as system clock */
76  using PLL = regval< regbits_type, 0x2 >; /**< 10: PLL selected as system clock */
77  };
78 
79  /** System clock switch status */
80  struct SWS
81  : public regbits< type, 2, 2 >
82  {
83  using HSI = regval< regbits_type, 0x0 >; /**< 00: HSI selected as system clock */
84  using HSE = regval< regbits_type, 0x1 >; /**< 01: HSE selected as system clock */
85  using PLL = regval< regbits_type, 0x2 >; /**< 10: PLL selected as system clock */
86  };
87 
88  /** AHB prescaler */
89  struct HPRE
90  : public regbits< type, 4, 4 >
91  {
92  using DIV1 = regval< regbits_type, 0x0 >; /**< 0xxx: SYSCLK not divided */
93  using DIV2 = regval< regbits_type, 0x8 >; /**< 1000: SYSCLK divided by 2 */
94  using DIV4 = regval< regbits_type, 0x9 >; /**< 1001: SYSCLK divided by 4 */
95  using DIV8 = regval< regbits_type, 0xa >; /**< 1010: SYSCLK divided by 8 */
96  using DIV16 = regval< regbits_type, 0xb >; /**< 1011: SYSCLK divided by 16 */
97  using DIV64 = regval< regbits_type, 0xc >; /**< 1100: SYSCLK divided by 64 */
98  using DIV128 = regval< regbits_type, 0xd >; /**< 1101: SYSCLK divided by 128 */
99  using DIV256 = regval< regbits_type, 0xe >; /**< 1110: SYSCLK divided by 256 */
100  using DIV512 = regval< regbits_type, 0xf >; /**< 1111: SYSCLK divided by 512 */
101  };
102 
103  /** APB low speed prescaler (APB1) */
104  struct PPRE1
105  : public regbits< type, 8, 3 >
106  {
107  using DIV1 = regval< regbits_type, 0x0 >; /**< 0xx: HCLK not divided */
108  using DIV2 = regval< regbits_type, 0x4 >; /**< 100: HCLK divided by 2 */
109  using DIV4 = regval< regbits_type, 0x5 >; /**< 101: HCLK divided by 4 */
110  using DIV8 = regval< regbits_type, 0x6 >; /**< 110: HCLK divided by 8 */
111  using DIV16 = regval< regbits_type, 0x7 >; /**< 111: HCLK divided by 16 */
112  };
113 
114  /** APB high speed prescaler (APB2) */
115  struct PPRE2
116  : public regbits< type, 11, 3 >
117  {
118  using DIV1 = regval< regbits_type, 0x0 >; /**< 0xx: HCLK not divided */
119  using DIV2 = regval< regbits_type, 0x4 >; /**< 100: HCLK divided by 2 */
120  using DIV4 = regval< regbits_type, 0x5 >; /**< 101: HCLK divided by 4 */
121  using DIV8 = regval< regbits_type, 0x6 >; /**< 110: HCLK divided by 8 */
122  using DIV16 = regval< regbits_type, 0x7 >; /**< 111: HCLK divided by 16 */
123  };
124 
125  /** ADC prescaler */
126  struct ADCPRE
127  : public regbits< type, 14, 2 >
128  {
129  using DIV2 = regval< regbits_type, 0x0 >; /**< 00: PCLK2 divided by 2 */
130  using DIV4 = regval< regbits_type, 0x1 >; /**< 01: PCLK2 divided by 4 */
131  using DIV6 = regval< regbits_type, 0x2 >; /**< 10: PCLK2 divided by 6 */
132  using DIV8 = regval< regbits_type, 0x3 >; /**< 11: PCLK2 divided by 8 */
133  };
134 
135  /** PLL entry clock source */
136  struct PLLSRC
137  : public regbits< type, 16, 1 >
138  {
139  using HSI_DIV2 = regval< regbits_type, 0x0 >; /**< 00: HSI clock divided by 2 selected as PLL input clock */
140  using HSE = regval< regbits_type, 0x1 >; /**< 01: HSE oscillator clock selected as PLL input clock (not available on connectivity line devices!) */
141  using PREDIV1 = regval< regbits_type, 0x1 >; /**< 01: Clock from PREDIV1 selected as PLL input clock (only available on connectivity line devices!) */
142  };
143 
144  /**
145  * - HSE divider for PLL entry (low-, medium-, high- and XL-density devices)
146  * - LSB of division factor PREDIV1 (connectivity line devices)
147  */
148  struct PLLXTPRE
149  : public regbits< type, 17, 1 >
150  {
151  /* Low-, medium-, high- and XL-density Devices */
152  using HSE_DIV1 = regval< regbits_type, 0x0 >; /**< 00: HSE clock not divided (not available on connectivity line devices!) */
153  using HSE_DIV2 = regval< regbits_type, 0x1 >; /**< 01: HSE clock divided by 2 (not available on connectivity line devices!) */
154 
155  /* Connectivity line devices */
156  using PREDIV1_DIV1 = regval< regbits_type, 0x0 >; /**< 00: PREDIV1 clock not divided for PLL entry (only available on connectivity line devices!) */
157  using PREDIV1_DIV2 = regval< regbits_type, 0x1 >; /**< 01: PREDIV1 clock divided by 2 for PLL entry (only available on connectivity line devices!) */
158  };
159 
160  /** PLL Multiplication Factor */
161  struct PLLMUL
162  : public regbits< type, 18, 4 >
163  {
164  using MUL2 = regval< regbits_type, 0x0 >; /**< 0000: PLL input clock * 2 (not available on connectivity line devices!) */
165  using MUL3 = regval< regbits_type, 0x1 >; /**< 0001: PLL input clock * 3 (not available on connectivity line devices!) */
166  using MUL4 = regval< regbits_type, 0x2 >; /**< 0010: PLL input clock * 4 */
167  using MUL5 = regval< regbits_type, 0x3 >; /**< 0011: PLL input clock * 5 */
168  using MUL6 = regval< regbits_type, 0x4 >; /**< 0100: PLL input clock * 6 */
169  using MUL7 = regval< regbits_type, 0x5 >; /**< 0101: PLL input clock * 7 */
170  using MUL8 = regval< regbits_type, 0x6 >; /**< 0110: PLL input clock * 8 */
171  using MUL9 = regval< regbits_type, 0x7 >; /**< 0111: PLL input clock * 9 */
172  using MUL10 = regval< regbits_type, 0x8 >; /**< 1000: PLL input clock * 10 (not available on connectivity line devices!) */
173  using MUL11 = regval< regbits_type, 0x9 >; /**< 1001: PLL input clock * 11 (not available on connectivity line devices!) */
174  using MUL12 = regval< regbits_type, 0xa >; /**< 1010: PLL input clock * 12 (not available on connectivity line devices!) */
175  using MUL13 = regval< regbits_type, 0xb >; /**< 1011: PLL input clock * 13 (not available on connectivity line devices!) */
176  using MUL14 = regval< regbits_type, 0xc >; /**< 1100: PLL input clock * 14 (not available on connectivity line devices!) */
177  using MUL15 = regval< regbits_type, 0xd >; /**< 1101: PLL input clock * 15 (not available on connectivity line devices!) */
178  using MUL16 = regval< regbits_type, 0xe >; /**< 1110: PLL input clock * 16 (not available on connectivity line devices!) */
179  using MUL6_5 = regval< regbits_type, 0xd >; /**< 1101: PLL input clock * 6.5 (only available on connectivity line devices!) */
180  };
181 
182  /** USB OTG FS prescaler (only available on connectivity line devices!) */
183  struct OTGFSPRE
184  : public regbits< type, 22, 1 >
185  {
186  using DIV3 = regval< regbits_type, 0x0 >;
187  using DIV2 = regval< regbits_type, 0x1 >;
188  };
189 
190  /** USB prescaler (not available on connectivity line devices!) */
191  struct USBPRE
192  : public regbits< type, 22, 1 >
193  {
194  using DIV1_5 = regval< regbits_type, 0x0 >;
195  using DIV1 = regval< regbits_type, 0x1 >;
196  };
197 
198  /** Microcontroller Clock Output */
199  struct MCO
200  : public regbits< type, 24, 4 >
201  {
202  using NOCLOCK = regval< regbits_type, 0x0 >; /**< 00xx: No clock */
203  using SYSCLK = regval< regbits_type, 0x4 >; /**< 0100: System clock selected */
204  using HSI = regval< regbits_type, 0x5 >; /**< 0101: HSI clock selected */
205  using HSE = regval< regbits_type, 0x6 >; /**< 0110: HSE clock selected */
206  using PLL_DIV2 = regval< regbits_type, 0x7 >; /**< 0111: PLL clock divided by 2 selected */
207  using PLL2 = regval< regbits_type, 0x8 >; /**< 1000: PLL2 clock selected (only available on connectivity line devices!) */
208  using PLL3_DIV2 = regval< regbits_type, 0x9 >; /**< 1001: PLL3 clock divided by 2 selected (only available on connectivity line devices!) */
209  using Ext_HSE = regval< regbits_type, 0xa >; /**< 1010: XT1 external 3-25 MHz oscillator clock selected (for Ethernet) (only available on connectivity line devices!) */
210  using PLL3 = regval< regbits_type, 0xb >; /**< 1011: PLL3 clock selected (for Ethernet) (only available on connectivity line devices!) */
211  };
212  };
213 
214  /**
215  * Clock interrupt register (RCC_CIR)
216  */
217  struct CIR
218  : public reg< uint32_t, base_addr + 0x8, rw, 0x00000000 >
219  {
220  using LSIRDYF = regbits< type, 0, 1 >; /**< LSI Ready Interrupt flag */
221  using LSERDYF = regbits< type, 1, 1 >; /**< LSE Ready Interrupt flag */
222  using HSIRDYF = regbits< type, 2, 1 >; /**< HSI Ready Interrupt flag */
223  using HSERDYF = regbits< type, 3, 1 >; /**< HSE Ready Interrupt flag */
224  using PLLRDYF = regbits< type, 4, 1 >; /**< PLL Ready Interrupt flag */
225  using PLL2RDYF = regbits< type, 5, 1 >; /**< PLL2 Ready Interrupt flag (only available on connectivity line devices!) */
226  using PLL3RDYF = regbits< type, 6, 1 >; /**< PLL3 Ready Interrupt flag (only available on connectivity line devices!) */
227  using CSSF = regbits< type, 7, 1 >; /**< Clock Security System Interrupt flag */
228  using LSIRDYIE = regbits< type, 8, 1 >; /**< LSI Ready Interrupt Enable */
229  using LSERDYIE = regbits< type, 9, 1 >; /**< LSE Ready Interrupt Enable */
230  using HSIRDYIE = regbits< type, 10, 1 >; /**< HSI Ready Interrupt Enable */
231  using HSERDYIE = regbits< type, 11, 1 >; /**< HSE Ready Interrupt Enable */
232  using PLLRDYIE = regbits< type, 12, 1 >; /**< PLL Ready Interrupt Enable */
233  using PLL2RDYIE = regbits< type, 13, 1 >; /**< PLL2 Ready Interrupt Enable (only available on connectivity line devices!) */
234  using PLL3RDYIE = regbits< type, 14, 1 >; /**< PLL3 Ready Interrupt Enable (only available on connectivity line devices!) */
235  using LSIRDYC = regbits< type, 16, 1 >; /**< LSI Ready Interrupt Clear */
236  using LSERDYC = regbits< type, 17, 1 >; /**< LSE Ready Interrupt Clear */
237  using HSIRDYC = regbits< type, 18, 1 >; /**< HSI Ready Interrupt Clear */
238  using HSERDYC = regbits< type, 19, 1 >; /**< HSE Ready Interrupt Clear */
239  using PLLRDYC = regbits< type, 20, 1 >; /**< PLL Ready Interrupt Clear */
240  using PLL2RDYC = regbits< type, 21, 1 >; /**< PLL2 Ready Interrupt Clear (only available on connectivity line devices!) */
241  using PLL3RDYC = regbits< type, 22, 1 >; /**< PLL3 Ready Interrupt Clear (only available on connectivity line devices!) */
242  using CSSC = regbits< type, 23, 1 >; /**< Clock security system interrupt clear */
243  };
244 
245  /**
246  * APB2 peripheral reset register (RCC_APB2RSTR)
247  */
248  struct APB2RSTR
249  : public reg< uint32_t, base_addr + 0xc, rw, 0x000000000 >
250  {
251  using AFIORST = regbits< type, 0, 1 >; /**< Alternate function I/O reset */
252  using IOPARST = regbits< type, 2, 1 >; /**< IO port A reset */
253  using IOPBRST = regbits< type, 3, 1 >; /**< IO port B reset */
254  using IOPCRST = regbits< type, 4, 1 >; /**< IO port C reset */
255  using IOPDRST = regbits< type, 5, 1 >; /**< IO port D reset */
256  using IOPERST = regbits< type, 6, 1 >; /**< IO port E reset (not available on low-density devices!) */
257  using IOPFRST = regbits< type, 7, 1 >; /**< IO port F reset (only available on high- and XL-density devices!) */
258  using IOPGRST = regbits< type, 8, 1 >; /**< IO port G reset (only available on high- and XL-density devices!) */
259  using ADC1RST = regbits< type, 9, 1 >; /**< ADC 1 interface reset */
260  using ADC2RST = regbits< type, 10, 1 >; /**< ADC 2 interface reset (not available on low- and medium-density devices!) */
261  using TIM1RST = regbits< type, 11, 1 >; /**< TIM1 timer reset */
262  using SPI1RST = regbits< type, 12, 1 >; /**< SPI 1 reset */
263  using TIM8RST = regbits< type, 13, 1 >; /**< TIM8 Timer reset (only available on high- and XL-density devices!) */
264  using USART1RST = regbits< type, 14, 1 >; /**< USART1 reset */
265  using ADC3RST = regbits< type, 15, 1 >; /**< ADC3 interface reset (only available on high- and XL-density devices!) */
266  using TIM15RST = regbits< type, 16, 1 >; /**< TIM15 Timer reset (only available on low- and medium-density devices!) */
267  using TIM16RST = regbits< type, 17, 1 >; /**< TIM16 Timer reset (only available on low- and medium-density devices!) */
268  using TIM17RST = regbits< type, 18, 1 >; /**< TIM17 Timer reset (only available on low- and medium-density devices!) */
269  using TIM9RST = regbits< type, 19, 1 >; /**< TIM9 Timer reset (only available on XL-density devices!) */
270  using TIM10RST = regbits< type, 20, 1 >; /**< TIM10 Timer reset (only available on XL-density devices!) */
271  using TIM11RST = regbits< type, 21, 1 >; /**< TIM11 Timer reset (only available on XL-density devices!) */
272  };
273 
274  /**
275  * APB1 peripheral reset register (RCC_APB1RSTR)
276  */
277  struct APB1RSTR
278  : public reg< uint32_t, base_addr + 0x10, rw, 0x00000000 >
279  {
280  using TIM2RST = regbits< type, 0, 1 >; /**< Timer 2 reset */
281  using TIM3RST = regbits< type, 1, 1 >; /**< Timer 3 reset */
282  using TIM4RST = regbits< type, 2, 1 >; /**< Timer 4 reset (not available on low-density devices!) */
283  using TIM5RST = regbits< type, 3, 1 >; /**< Timer 5 reset */
284  using TIM6RST = regbits< type, 4, 1 >; /**< Timer 6 reset */
285  using TIM7RST = regbits< type, 5, 1 >; /**< Timer 7 reset */
286  using TIM12RST = regbits< type, 6, 1 >; /**< Timer 12 reset (only available on XL-density devices!) */
287  using TIM13RST = regbits< type, 7, 1 >; /**< Timer 13 reset (only available on XL-density devices!) */
288  using TIM14RST = regbits< type, 8, 1 >; /**< Timer 14 reset (only available on XL-density devices!) */
289  using WWDGRST = regbits< type, 11, 1 >; /**< Window Watchdog reset */
290  using SPI2RST = regbits< type, 14, 1 >; /**< SPI 2 reset (not available on low-density devices!) */
291  using SPI3RST = regbits< type, 15, 1 >; /**< SPI 3 reset */
292  using USART2RST = regbits< type, 17, 1 >; /**< USART 2 reset */
293  using USART3RST = regbits< type, 18, 1 >; /**< RUSART 3 reset (not available on low-density devices!) */
294  using UART4RST = regbits< type, 19, 1 >; /**< UART 4 reset */
295  using UART5RST = regbits< type, 20, 1 >; /**< UART 5 reset */
296  using I2C1RST = regbits< type, 21, 1 >; /**< I2C 1 reset */
297  using I2C2RST = regbits< type, 22, 1 >; /**< I2C 2 reset (not available on low-density devices!) */
298  using USBRST = regbits< type, 23, 1 >; /**< USB Device reset (not available on connectivity line devices!) */
299  using CAN1RST = regbits< type, 25, 1 >; /**< CAN1 reset (not available on low- and medium-density devices!) */
300  using CAN2RST = regbits< type, 26, 1 >; /**< CAN2 reset (only available on connectivity line devices!) */
301  using BKPRST = regbits< type, 27, 1 >; /**< Backup interface reset */
302  using PWRRST = regbits< type, 28, 1 >; /**< Power interface reset */
303  using DACRST = regbits< type, 29, 1 >; /**< DAC interface reset */
304  using CECRST = regbits< type, 30, 1 >; /**< CEC interface reset */
305  };
306 
307  /**
308  * AHB Peripheral Clock enable register (RCC_AHBENR)
309  */
310  struct AHBENR
311  : public reg< uint32_t, base_addr + 0x14, rw, 0x00000014 >
312  {
313  using DMA1EN = regbits< type, 0, 1 >; /**< DMA1 clock enable */
314  using DMA2EN = regbits< type, 1, 1 >; /**< DMA2 clock enable (only available on high-density and connectivity line devices!) */
315  using SRAMEN = regbits< type, 2, 1 >; /**< SRAM interface clock enable */
316  using FLITFEN = regbits< type, 4, 1 >; /**< FLITF clock enable */
317  using CRCEN = regbits< type, 6, 1 >; /**< CRC clock enable */
318  using FSMCEN = regbits< type, 8, 1 >; /**< FSMC clock enable (only available on high- and XL-density devices!) */
319  using SDIOEN = regbits< type, 10, 1 >; /**< SDIO clock enable (only available on high- and XL-density devices!) */
320  using OTGFSEN = regbits< type, 12, 1 >; /**< USB OTG FS clock enable (only available on connectivity line devices!) */
321  using ETHMACEN = regbits< type, 14, 1 >; /**< Ethernet MAC clock enable (only available on connectivity line devices!) */
322  using ETHMACTXEN = regbits< type, 15, 1 >; /**< Ethernet MAC TX clock enable (only available on connectivity line devices!) */
323  using ETHMACRXEN = regbits< type, 16, 1 >; /**< Ethernet MAC RX clock enable (only available on connectivity line devices!) */
324  };
325 
326  /**
327  * APB2 peripheral clock enable register (RCC_APB2ENR)
328  */
329  struct APB2ENR
330  : public reg< uint32_t, base_addr + 0x18, rw, 0x00000000 >
331  {
332  using AFIOEN = regbits< type, 0, 1 >; /**< Alternate function I/O clock enable */
333  using IOPAEN = regbits< type, 2, 1 >; /**< I/O port A clock enable */
334  using IOPBEN = regbits< type, 3, 1 >; /**< I/O port B clock enable */
335  using IOPCEN = regbits< type, 4, 1 >; /**< I/O port C clock enable */
336  using IOPDEN = regbits< type, 5, 1 >; /**< I/O port D clock enable */
337  using IOPEEN = regbits< type, 6, 1 >; /**< I/O port E clock enable (not available on low-density devices!) */
338  using IOPFEN = regbits< type, 7, 1 >; /**< I/O port F clock enable (only available on high- and XL-density devices!) */
339  using IOPGEN = regbits< type, 8, 1 >; /**< I/O port G clock enable (only available on high- and XL-density devices!) */
340  using ADC1EN = regbits< type, 9, 1 >; /**< ADC 1 interface clock enable */
341  using ADC2EN = regbits< type, 10, 1 >; /**< ADC 2 interface clock enable (not available on low- and medium-density devices!) */
342  using TIM1EN = regbits< type, 11, 1 >; /**< TIM1 Timer clock enable */
343  using SPI1EN = regbits< type, 12, 1 >; /**< SPI 1 clock enable */
344  using TIM8EN = regbits< type, 13, 1 >; /**< TIM8 Timer clock enable (only available on high- and XL-density devices!) */
345  using USART1EN = regbits< type, 14, 1 >; /**< USART1 clock enable */
346  using ADC3EN = regbits< type, 15, 1 >; /**< ADC 3 interface clock enable (only available on high- and XL-density devices!) */
347  using TIM15EN = regbits< type, 16, 1 >; /**< TIM15 Timer clock enable (only available on low- and medium-density devices!) */
348  using TIM16EN = regbits< type, 17, 1 >; /**< TIM16 Timer clock enable (only available on low- and medium-density devices!) */
349  using TIM17EN = regbits< type, 18, 1 >; /**< TIM17 Timer clock enable (only available on low- and medium-density devices!) */
350  using TIM9EN = regbits< type, 19, 1 >; /**< TIM9 Timer clock enable (only available on XL-density devices!) */
351  using TIM10EN = regbits< type, 20, 1 >; /**< TIM10 Timer clock enable (only available on XL-density devices!) */
352  using TIM11EN = regbits< type, 21, 1 >; /**< TIM11 Timer clock enable (only available on XL-density devices!) */
353  };
354 
355  /**
356  * APB1 peripheral clock enable register (RCC_APB1ENR)
357  */
358  struct APB1ENR
359  : public reg< uint32_t, base_addr + 0x1c, rw, 0x00000000 >
360  {
361  using TIM2EN = regbits< type, 0, 1 >; /**< Timer 2 clock enable */
362  using TIM3EN = regbits< type, 1, 1 >; /**< Timer 3 clock enable */
363  using TIM4EN = regbits< type, 2, 1 >; /**< Timer 4 clock enable (not available on low-density devices!) */
364  using TIM5EN = regbits< type, 3, 1 >; /**< Timer 5 clock enable */
365  using TIM6EN = regbits< type, 4, 1 >; /**< Timer 6 clock enable */
366  using TIM7EN = regbits< type, 5, 1 >; /**< Timer 7 clock enable */
367  using TIM12EN = regbits< type, 6, 1 >; /**< Timer 12 clock enable (only available on XL-density devices!) */
368  using TIM13EN = regbits< type, 7, 1 >; /**< Timer 13 clock enable (only available on XL-density devices!) */
369  using TIM14EN = regbits< type, 8, 1 >; /**< Timer 14 clock enable (only available on XL-density devices!) */
370  using WWDGEN = regbits< type, 11, 1 >; /**< Window watchdog clock enable */
371  using SPI2EN = regbits< type, 14, 1 >; /**< SPI 2 clock enable (not available on low-density devices!) */
372  using SPI3EN = regbits< type, 15, 1 >; /**< SPI 3 clock enable */
373  using USART2EN = regbits< type, 17, 1 >; /**< USART 2 clock enable */
374  using USART3EN = regbits< type, 18, 1 >; /**< USART 3 clock enable (not available on low-density devices!) */
375  using UART4EN = regbits< type, 19, 1 >; /**< UART 4 clock enable */
376  using UART5EN = regbits< type, 20, 1 >; /**< UART 5 clock enable */
377  using I2C1EN = regbits< type, 21, 1 >; /**< I2C 1 clock enable */
378  using I2C2EN = regbits< type, 22, 1 >; /**< I2C 2 clock enable (not available on low-density devices!) */
379  using USBEN = regbits< type, 23, 1 >; /**< USB device clock enable (not available on connectivity line devices!) */
380  using CAN1EN = regbits< type, 25, 1 >; /**< CAN1 clock enable (not available on low- and medium-density devices!) */
381  using CAN2EN = regbits< type, 26, 1 >; /**< CAN2 clock enable (only available on connectivity line devices!) */
382  using BKPEN = regbits< type, 27, 1 >; /**< Backup interface clock enable */
383  using PWREN = regbits< type, 28, 1 >; /**< Power interface clock enable */
384  using DACEN = regbits< type, 29, 1 >; /**< DAC interface clock enable */
385  using CECEN = regbits< type, 30, 1 >; /**< CEC interface clock enable */
386 
387  };
388 
389  /**
390  * Backup domain control register (RCC_BDCR)
391  */
392  struct BDCR
393  : public reg< uint32_t, base_addr + 0x20, rw, 0x00000000 >
394  {
395  using LSEON = regbits< type, 0, 1 >; /**< External Low Speed oscillator enable */
396  using LSERDY = regbits< type, 1, 1 >; /**< External Low Speed oscillator ready */
397  using LSEBYP = regbits< type, 2, 1 >; /**< External Low Speed oscillator bypass */
398 
399  /** RTC clock source selection */
400  struct RTCSEL
401  : public regbits< type, 8, 2 >
402  {
403  using LSE = regval< regbits_type, 0x1 >; /**< 01: LSE oscillator clock used as RTC clock */
404  using LSI = regval< regbits_type, 0x2 >; /**< 10: LSI oscillator clock used as RTC clock */
405  using HSE = regval< regbits_type, 0x3 >; /**< 11: HSE oscillator clock divided by 128 used as RTC clock */
406  };
407 
408  using RTCEN = regbits< type, 15, 1 >; /**< RTC clock enable */
409  using BDRST = regbits< type, 16, 1 >; /**< Backup domain software reset */
410  };
411 
412  /**
413  * Control/status register (RCC_CSR)
414  */
415  struct CSR
416  : public reg< uint32_t, base_addr + 0x24, rw, 0x0C000000 >
417  {
418  using LSION = regbits< type, 0, 1 >; /**< Internal low speed oscillator enable */
419  using LSIRDY = regbits< type, 1, 1 >; /**< Internal low speed oscillator ready */
420  using RMVF = regbits< type, 24, 1 >; /**< Remove reset flag */
421  using PINRSTF = regbits< type, 26, 1 >; /**< PIN reset flag */
422  using PORRSTF = regbits< type, 27, 1 >; /**< POR/PDR reset flag */
423  using SFTRSTF = regbits< type, 28, 1 >; /**< Software reset flag */
424  using IWDGRSTF = regbits< type, 29, 1 >; /**< Independent watchdog reset flag */
425  using WWDGRSTF = regbits< type, 30, 1 >; /**< Window watchdog reset flag */
426  using LPWRRSTF = regbits< type, 31, 1 >; /**< Low-power reset flag */
427  };
428 
429  /**
430  * AHB peripheral clock reset register (RCC_AHBRSTR)
431  * (only available on connectivity line devices!)
432  */
433  struct AHBRSTR
434  : public reg< uint32_t, base_addr + 0x28, rw, 0x00000000 >
435  {
436  using OTGFSRST = regbits< type, 12, 1 >; /**< USB OTG FS reset */
437  using ETHMACRST = regbits< type, 14, 1 >; /**< Ethernet MAC reset */
438  };
439 
440  /**
441  * Clock configuration register2 (RCC_CFGR2)
442  * (only available on connectivity line devices!)
443  */
444  struct CFGR2
445  : public reg< uint32_t, base_addr + 0x2c, rw, 0x00000000 >
446  {
447  using PREDIV1 = regbits< type, 0, 4 >; /**< PREDIV1 division factor */
448  using PREDIV2 = regbits< type, 4, 4 >; /**< PREDIV2 division factor */
449  using PLL2MUL = regbits< type, 8, 4 >; /**< PLL2 Multiplication Factor */
450  using PLL3MUL = regbits< type, 12, 4 >; /**< PLL3 Multiplication Factor */
451 
452  /** PREDIV1 entry clock source */
453  struct PREDIV1SRC
454  : public regbits< type, 16, 1 >
455  {
456  using HSE = regval< regbits_type, 0x0 >; /**< 0: HSE oscillator clock selected as PREDIV1 clock entry */
457  using PLL2 = regval< regbits_type, 0x1 >; /**< 1: PLL2 selected as PREDIV1 clock entry */
458  };
459 
460  /** I2S2 clock source */
461  struct I2S2SRC
462  : public regbits< type, 17, 1 >
463  {
464  using SYSCLK = regval< regbits_type, 0x0 >; /**< 0: System clock (SYSCLK) selected as I2Sx clock entry */
465  using PLL3 = regval< regbits_type, 0x1 >; /**< 1: PLL3 VCO clock selected as I2Sx clock entry */
466  };
467 
468  /** I2S3 clock source */
469  struct I2S3SRC
470  : public regbits< type, 18, 1 >
471  {
472  using SYSCLK = regval< regbits_type, 0x0 >; /**< 0: System clock (SYSCLK) selected as I2S3 clock entry */
473  using PLL3 = regval< regbits_type, 0x1 >; /**< 1: PLL3 VCO clock selected as I2S3 clock entry */
474  };
475  };
476 };
477 
478 } // namespace mptl
479 
480 #endif // ARCH_REG_RCC_HPP_INCLUDED
mptl::RCC::CFGR
Clock configuration register (RCC_CFGR)
Definition: rcc.hpp:67
mptl::RCC::base_addr
static constexpr reg_addr_t base_addr
Definition: rcc.hpp:40
mptl::RCC::APB2ENR
APB2 peripheral clock enable register (RCC_APB2ENR)
Definition: rcc.hpp:329
mptl::RCC::AHBRSTR
AHB peripheral clock reset register (RCC_AHBRSTR) (only available on connectivity line devices!) ...
Definition: rcc.hpp:433
mptl::RCC::CFGR::USBPRE
USB prescaler (not available on connectivity line devices!)
Definition: rcc.hpp:191
mptl::RCC::CFGR::SWS
System clock switch status.
Definition: rcc.hpp:80
mptl::reg_addr_t
uintptr_t reg_addr_t
mptl::RCC::CFGR::PLLSRC
PLL entry clock source.
Definition: rcc.hpp:136
mptl::RCC::CFGR::PPRE1
APB low speed prescaler (APB1)
Definition: rcc.hpp:104
mptl::RCC::CFGR::MCO
Microcontroller Clock Output.
Definition: rcc.hpp:199
mptl::RCC::BDCR
Backup domain control register (RCC_BDCR)
Definition: rcc.hpp:392
mptl::RCC::CSR
Control/status register (RCC_CSR)
Definition: rcc.hpp:415
mptl::RCC::CFGR::HPRE
AHB prescaler.
Definition: rcc.hpp:89
mptl::RCC::AHBENR
AHB Peripheral Clock enable register (RCC_AHBENR)
Definition: rcc.hpp:310
mptl::RCC::CFGR2::I2S3SRC
I2S3 clock source.
Definition: rcc.hpp:469
mptl::RCC::CIR
Clock interrupt register (RCC_CIR)
Definition: rcc.hpp:217
mptl::RCC::CR
Clock control register.
Definition: rcc.hpp:45
mptl::RCC::CFGR::PPRE2
APB high speed prescaler (APB2)
Definition: rcc.hpp:115
mptl::RCC::BDCR::RTCSEL
RTC clock source selection.
Definition: rcc.hpp:400
mptl::RCC::APB1RSTR
APB1 peripheral reset register (RCC_APB1RSTR)
Definition: rcc.hpp:277
mptl::RCC::APB2RSTR
APB2 peripheral reset register (RCC_APB2RSTR)
Definition: rcc.hpp:248
mptl::RCC::CFGR::PLLXTPRE
Definition: rcc.hpp:148
mptl::RCC::CFGR::ADCPRE
ADC prescaler.
Definition: rcc.hpp:126
mptl::RCC::CFGR2::I2S2SRC
I2S2 clock source.
Definition: rcc.hpp:461
mptl::RCC::CFGR::SW
System clock switch.
Definition: rcc.hpp:71
mptl::RCC::CFGR::PLLMUL
PLL Multiplication Factor.
Definition: rcc.hpp:161
mptl::RCC::APB1ENR
APB1 peripheral clock enable register (RCC_APB1ENR)
Definition: rcc.hpp:358
mptl::RCC::CFGR2::PREDIV1SRC
PREDIV1 entry clock source.
Definition: rcc.hpp:453
mptl::RCC
Reset and clock control.
Definition: rcc.hpp:38
mptl::RCC::CFGR2
Clock configuration register2 (RCC_CFGR2) (only available on connectivity line devices!) ...
Definition: rcc.hpp:444
mptl::RCC::CFGR::OTGFSPRE
USB OTG FS prescaler (only available on connectivity line devices!)
Definition: rcc.hpp:183
Generated by   doxygen 1.8.13