Clock control register.
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| using | PLLI2SRDY = regbits< type, 27, 1 > |
| | PLLI2S clock ready flag. More...
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| using | PLLI2SON = regbits< type, 26, 1 > |
| | PLLI2S enable. More...
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| using | PLLRDY = regbits< type, 25, 1 > |
| | Main PLL clock ready flag. More...
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| using | PLLON = regbits< type, 24, 1 > |
| | Main PLL enable. More...
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| |
| using | CSSON = regbits< type, 19, 1 > |
| | Clock security system enable. More...
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| using | HSEBYP = regbits< type, 18, 1 > |
| | HSE clock bypass. More...
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| using | HSERDY = regbits< type, 17, 1 > |
| | HSE clock ready flag. More...
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| using | HSEON = regbits< type, 16, 1 > |
| | HSE clock enable. More...
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| using | HSICAL = regbits< type, 8, 8 > |
| | Internal high-speed clock calibration. More...
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| using | HSITRIM = regbits< type, 3, 5 > |
| | Internal high-speed clock trimming. More...
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| |
| using | HSIRDY = regbits< type, 1, 1 > |
| | Internal high-speed clock ready flag. More...
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| |
| using | HSION = regbits< type, 0, 1 > |
| | Internal high-speed clock enable. More...
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| |
| typedef reg< Tp, base_addr+0x00, rw, 0x00000083 > | type |
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| typedef type | reg_type |
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| typedef regbits< type, 0, sizeof(Tp) *8 > | regbits_type |
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| typedef Tp | value_type |
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| typedef regmask< reg_type, 0, 0 > | neutral_regmask |
| |
| typedef Tp | value_type |
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