OpenMPTL - STM32F4
C++ Microprocessor Template Library
rcc.hpp
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1 /*
2  * OpenMPTL - C++ Microprocessor Template Library
3  *
4  * Copyright (C) 2012-2017 Axel Burri <axel@tty0.ch>
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License as published by
8  * the Free Software Foundation; either version 3 of the License, or
9  * (at your option) any later version.
10  *
11  * This program is distributed in the hope that it will be useful,
12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14  * GNU General Public License for more details.
15  *
16  * You should have received a copy of the GNU General Public License
17  * along with this program. If not, see <http://www.gnu.org/licenses/>.
18  *
19  */
20 
21 /*
22  * This program contains derivative representations of CMSIS System
23  * View Description (SVD) files, and is subject to the "End User
24  * License Agreement for STMicroelectronics" (see "STM_License.html"
25  * in the containing directory).
26  */
27 
28 #ifndef ARCH_REG_RCC_HPP_INCLUDED
29 #define ARCH_REG_RCC_HPP_INCLUDED
30 
31 #include <register.hpp>
32 
33 namespace mptl {
34 
35 /**
36  * Reset and clock control
37  */
38 struct RCC
39 {
40  static constexpr reg_addr_t base_addr = 0x40023800;
41 
42  /**
43  * Clock control register
44  */
45  struct CR
46  : public reg< uint32_t, base_addr + 0x00, rw, 0x00000083 >
47  {
48  using PLLI2SRDY = regbits< type, 27, 1 >; /**< PLLI2S clock ready flag */
49  using PLLI2SON = regbits< type, 26, 1 >; /**< PLLI2S enable */
50  using PLLRDY = regbits< type, 25, 1 >; /**< Main PLL clock ready flag */
51  using PLLON = regbits< type, 24, 1 >; /**< Main PLL enable */
52  using CSSON = regbits< type, 19, 1 >; /**< Clock security system enable */
53  using HSEBYP = regbits< type, 18, 1 >; /**< HSE clock bypass */
54  using HSERDY = regbits< type, 17, 1 >; /**< HSE clock ready flag */
55  using HSEON = regbits< type, 16, 1 >; /**< HSE clock enable */
56  using HSICAL = regbits< type, 8, 8 >; /**< Internal high-speed clock calibration */
57  using HSITRIM = regbits< type, 3, 5 >; /**< Internal high-speed clock trimming */
58  using HSIRDY = regbits< type, 1, 1 >; /**< Internal high-speed clock ready flag */
59  using HSION = regbits< type, 0, 1 >; /**< Internal high-speed clock enable */
60  };
61 
62  /**
63  * PLL configuration register
64  */
65  struct PLLCFGR
66  : public reg< uint32_t, base_addr + 0x04, rw, 0x24003010 >
67  {
68  using PLLQ = regbits< type, 24, 4 >; /**< Main PLL division factor for USB OTG FS, SDIO and random number generator clocks */
69  using PLLSRC = regbits< type, 22, 1 >; /**< Main PLL and audio PLL entry clock source */
70  using PLLP = regbits< type, 16, 2 >; /**< Main PLL division factor for main system clock */
71  using PLLN = regbits< type, 6, 9 >; /**< Main PLL multiplication factor for VCO */
72  using PLLM = regbits< type, 0, 6 >; /**< Division factor for the main PLL and audio PLL input clock */
73  };
74 
75  /**
76  * Clock configuration register
77  */
78  struct CFGR
79  : public reg< uint32_t, base_addr + 0x08, rw, 0x00000000 >
80  {
81  /** APB1/2 prescaler */
82  template<typename Rb>
83  struct __PPREx
84  : public Rb
85  {
86  using DIV1 = regval< Rb, 0x0 >; /**< 0xx: AHB clock not divided */
87  using DIV2 = regval< Rb, 0x4 >; /**< 100: AHB clock divided by 2 */
88  using DIV4 = regval< Rb, 0x5 >; /**< 101: AHB clock divided by 4 */
89  using DIV8 = regval< Rb, 0x6 >; /**< 110: AHB clock divided by 8 */
90  using DIV16 = regval< Rb, 0x7 >; /**< 111: AHB clock divided by 16 */
91  };
92 
93  /** AHB prescaler */
94  template<typename Rb>
95  struct __HPRE
96  : public Rb
97  {
98  using DIV1 = regval< Rb, 0x0 >; /**< 0xxx: system clock not divided */
99  using DIV2 = regval< Rb, 0x8 >; /**< 1000: system clock divided by 2 */
100  using DIV4 = regval< Rb, 0x9 >; /**< 1001: system clock divided by 4 */
101  using DIV8 = regval< Rb, 0xA >; /**< 1010: system clock divided by 8 */
102  using DIV16 = regval< Rb, 0xB >; /**< 1011: system clock divided by 16 */
103  using DIV64 = regval< Rb, 0xC >; /**< 1100: system clock divided by 64 */
104  using DIV128 = regval< Rb, 0xD >; /**< 1101: system clock divided by 128 */
105  using DIV256 = regval< Rb, 0xE >; /**< 1110: system clock divided by 256 */
106  using DIV512 = regval< Rb, 0xF >; /**< 1111: system clock divided by 512 */
107  };
108 
109  /** System clock Switch */
110  template<typename Rb>
111  struct __SWx
112  : public Rb
113  {
114  using HSI = regval< Rb, 0x0 >; /**< 00: HSI selected as system clock */
115  using HSE = regval< Rb, 0x1 >; /**< 01: HSE selected as system clock */
116  using PLL = regval< Rb, 0x2 >; /**< 10: PLL selected as system clock */
117  };
118 
119  using MCO2 = regbits< type, 30, 2 >; /**< Microcontroller clock output 2 */
120  using MCO2PRE = regbits< type, 27, 3 >; /**< MCO2 prescaler */
121  using MCO1PRE = regbits< type, 24, 3 >; /**< MCO1 prescaler */
122  using I2SSRC = regbits< type, 23, 1 >; /**< I2S clock selection */
123  using MCO1 = regbits< type, 21, 2 >; /**< Microcontroller clock output 1 */
124  using RTCPRE = regbits< type, 16, 5 >; /**< HSE division factor for RTC clock */
125  using PPRE2 = __PPREx < regbits< type, 13, 3 > >; /**< APB high-speed prescaler (APB2) */
126  using PPRE1 = __PPREx < regbits< type, 10, 3 > >; /**< APB low-speed prescaler (APB1) */
127  using HPRE = __HPRE < regbits< type, 4, 4 > >; /**< AHB prescaler */
128  using SWS = __SWx < regbits< type, 2, 2 > >; /**< System clock switch status */
129  using SW = __SWx < regbits< type, 0, 2 > >; /**< System clock switch */
130  };
131 
132  /**
133  * Clock interrupt register
134  */
135  struct CIR
136  : public reg< uint32_t, base_addr + 0x0C, rw, 0x00000000 >
137  {
138  using CSSC = regbits< type, 23, 1 >; /**< Clock security system interrupt clear */
139  using PLLI2SRDYC = regbits< type, 21, 1 >; /**< PLLI2S ready interrupt clear */
140  using PLLRDYC = regbits< type, 20, 1 >; /**< Main PLL ready interrupt clear */
141  using HSERDYC = regbits< type, 19, 1 >; /**< HSE ready interrupt clear */
142  using HSIRDYC = regbits< type, 18, 1 >; /**< HSI ready interrupt clear */
143  using LSERDYC = regbits< type, 17, 1 >; /**< LSE ready interrupt clear */
144  using LSIRDYC = regbits< type, 16, 1 >; /**< LSI ready interrupt clear */
145  using PLLI2SRDYIE = regbits< type, 13, 1 >; /**< PLLI2S ready interrupt enable */
146  using PLLRDYIE = regbits< type, 12, 1 >; /**< Main PLL ready interrupt enable */
147  using HSERDYIE = regbits< type, 11, 1 >; /**< HSE ready interrupt enable */
148  using HSIRDYIE = regbits< type, 10, 1 >; /**< HSI ready interrupt enable */
149  using LSERDYIE = regbits< type, 9, 1 >; /**< LSE ready interrupt enable */
150  using LSIRDYIE = regbits< type, 8, 1 >; /**< LSI ready interrupt enable */
151  using CSSF = regbits< type, 7, 1 >; /**< Clock security system interrupt flag */
152  using PLLI2SRDYF = regbits< type, 5, 1 >; /**< PLLI2S ready interrupt flag */
153  using PLLRDYF = regbits< type, 4, 1 >; /**< Main PLL ready interrupt flag */
154  using HSERDYF = regbits< type, 3, 1 >; /**< HSE ready interrupt flag */
155  using HSIRDYF = regbits< type, 2, 1 >; /**< HSI ready interrupt flag */
156  using LSERDYF = regbits< type, 1, 1 >; /**< LSE ready interrupt flag */
157  using LSIRDYF = regbits< type, 0, 1 >; /**< LSI ready interrupt flag */
158  };
159 
160  /**
161  * AHB1 peripheral reset register
162  */
163  struct AHB1RSTR
164  : public reg< uint32_t, base_addr + 0x10, rw, 0x00000000 >
165  {
166  using OTGHSRST = regbits< type, 29, 1 >; /**< USB OTG HS module reset */
167  using ETHMACRST = regbits< type, 25, 1 >; /**< Ethernet MAC reset */
168  using DMA2RST = regbits< type, 22, 1 >; /**< DMA2 reset */
169  using DMA1RST = regbits< type, 21, 1 >; /**< DMA1 reset */
170  using CRCRST = regbits< type, 12, 1 >; /**< CRC reset */
171  using GPIOIRST = regbits< type, 8, 1 >; /**< IO port I reset */
172  using GPIOHRST = regbits< type, 7, 1 >; /**< IO port H reset */
173  using GPIOGRST = regbits< type, 6, 1 >; /**< IO port G reset */
174  using GPIOFRST = regbits< type, 5, 1 >; /**< IO port F reset */
175  using GPIOERST = regbits< type, 4, 1 >; /**< IO port E reset */
176  using GPIODRST = regbits< type, 3, 1 >; /**< IO port D reset */
177  using GPIOCRST = regbits< type, 2, 1 >; /**< IO port C reset */
178  using GPIOBRST = regbits< type, 1, 1 >; /**< IO port B reset */
179  using GPIOARST = regbits< type, 0, 1 >; /**< IO port A reset */
180  };
181 
182  /**
183  * AHB2 peripheral reset register
184  */
185  struct AHB2RSTR
186  : public reg< uint32_t, base_addr + 0x14, rw, 0x00000000 >
187  {
188  using OTGFSRST = regbits< type, 7, 1 >; /**< USB OTG FS module reset */
189  using RNGRST = regbits< type, 6, 1 >; /**< Random number generator module reset */
190  using DCMIRST = regbits< type, 0, 1 >; /**< Camera interface reset */
191  };
192 
193  /**
194  * AHB3 peripheral reset register
195  */
196  struct AHB3RSTR
197  : public reg< uint32_t, base_addr + 0x18, rw, 0x00000000 >
198  {
199  using FSMCRST = regbits< type, 0, 1 >; /**< Flexible static memory controller module reset */
200  };
201 
202  /**
203  * APB1 peripheral reset register
204  */
205  struct APB1RSTR
206  : public reg< uint32_t, base_addr + 0x20, rw, 0x00000000 >
207  {
208  using DACRST = regbits< type, 29, 1 >; /**< DAC reset */
209  using PWRRST = regbits< type, 28, 1 >; /**< Power interface reset */
210  using CAN2RST = regbits< type, 26, 1 >; /**< CAN2 reset */
211  using CAN1RST = regbits< type, 25, 1 >; /**< CAN1 reset */
212  using I2C3RST = regbits< type, 23, 1 >; /**< I2C3 reset */
213  using I2C2RST = regbits< type, 22, 1 >; /**< I2C 2 reset */
214  using I2C1RST = regbits< type, 21, 1 >; /**< I2C 1 reset */
215  using UART5RST = regbits< type, 20, 1 >; /**< USART 5 reset */
216  using UART4RST = regbits< type, 19, 1 >; /**< USART 4 reset */
217  using UART3RST = regbits< type, 18, 1 >; /**< USART 3 reset */
218  using UART2RST = regbits< type, 17, 1 >; /**< USART 2 reset */
219  using SPI3RST = regbits< type, 15, 1 >; /**< SPI 3 reset */
220  using SPI2RST = regbits< type, 14, 1 >; /**< SPI 2 reset */
221  using WWDGRST = regbits< type, 11, 1 >; /**< Window watchdog reset */
222  using TIM14RST = regbits< type, 8, 1 >; /**< TIM14 reset */
223  using TIM13RST = regbits< type, 7, 1 >; /**< TIM13 reset */
224  using TIM12RST = regbits< type, 6, 1 >; /**< TIM12 reset */
225  using TIM7RST = regbits< type, 5, 1 >; /**< TIM7 reset */
226  using TIM6RST = regbits< type, 4, 1 >; /**< TIM6 reset */
227  using TIM5RST = regbits< type, 3, 1 >; /**< TIM5 reset */
228  using TIM4RST = regbits< type, 2, 1 >; /**< TIM4 reset */
229  using TIM3RST = regbits< type, 1, 1 >; /**< TIM3 reset */
230  using TIM2RST = regbits< type, 0, 1 >; /**< TIM2 reset */
231  };
232 
233  /**
234  * APB2 peripheral reset register
235  */
236  struct APB2RSTR
237  : public reg< uint32_t, base_addr + 0x24, rw, 0x00000000 >
238  {
239  using TIM11RST = regbits< type, 18, 1 >; /**< TIM11 reset */
240  using TIM10RST = regbits< type, 17, 1 >; /**< TIM10 reset */
241  using TIM9RST = regbits< type, 16, 1 >; /**< TIM9 reset */
242  using SYSCFGRST = regbits< type, 14, 1 >; /**< System configuration controller reset */
243  using SPI1RST = regbits< type, 12, 1 >; /**< SPI 1 reset */
244  using SDIORST = regbits< type, 11, 1 >; /**< SDIO reset */
245  using ADCRST = regbits< type, 8, 1 >; /**< ADC interface reset (common to all ADCs) */
246  using USART6RST = regbits< type, 5, 1 >; /**< USART6 reset */
247  using USART1RST = regbits< type, 4, 1 >; /**< USART1 reset */
248  using TIM8RST = regbits< type, 1, 1 >; /**< TIM8 reset */
249  using TIM1RST = regbits< type, 0, 1 >; /**< TIM1 reset */
250  };
251 
252  /**
253  * AHB1 peripheral clock register
254  */
255  struct AHB1ENR
256  : public reg< uint32_t, base_addr + 0x30, rw, 0x00100000 >
257  {
258  using OTGHSULPIEN = regbits< type, 30, 1 >; /**< USB OTG HSULPI clock enable */
259  using OTGHSEN = regbits< type, 29, 1 >; /**< USB OTG HS clock enable */
260  using ETHMACPTPEN = regbits< type, 28, 1 >; /**< Ethernet PTP clock enable */
261  using ETHMACRXEN = regbits< type, 27, 1 >; /**< Ethernet Reception clock enable */
262  using ETHMACTXEN = regbits< type, 26, 1 >; /**< Ethernet Transmission clock enable */
263  using ETHMACEN = regbits< type, 25, 1 >; /**< Ethernet MAC clock enable */
264  using DMA2EN = regbits< type, 22, 1 >; /**< DMA2 clock enable */
265  using DMA1EN = regbits< type, 21, 1 >; /**< DMA1 clock enable */
266  using BKPSRAMEN = regbits< type, 18, 1 >; /**< Backup SRAM interface clock enable */
267  using CRCEN = regbits< type, 12, 1 >; /**< CRC clock enable */
268  using GPIOIEN = regbits< type, 8, 1 >; /**< IO port I clock enable */
269  using GPIOHEN = regbits< type, 7, 1 >; /**< IO port H clock enable */
270  using GPIOGEN = regbits< type, 6, 1 >; /**< IO port G clock enable */
271  using GPIOFEN = regbits< type, 5, 1 >; /**< IO port F clock enable */
272  using GPIOEEN = regbits< type, 4, 1 >; /**< IO port E clock enable */
273  using GPIODEN = regbits< type, 3, 1 >; /**< IO port D clock enable */
274  using GPIOCEN = regbits< type, 2, 1 >; /**< IO port C clock enable */
275  using GPIOBEN = regbits< type, 1, 1 >; /**< IO port B clock enable */
276  using GPIOAEN = regbits< type, 0, 1 >; /**< IO port A clock enable */
277  };
278 
279  /**
280  * AHB2 peripheral clock enable register
281  */
282  struct AHB2ENR
283  : public reg< uint32_t, base_addr + 0x34, rw, 0x00000000 >
284  {
285  using OTGFSEN = regbits< type, 7, 1 >; /**< USB OTG FS clock enable */
286  using RNGEN = regbits< type, 6, 1 >; /**< Random number generator clock enable */
287  using DCMIEN = regbits< type, 0, 1 >; /**< Camera interface enable */
288  };
289 
290  /**
291  * AHB3 peripheral clock enable register
292  */
293  struct AHB3ENR
294  : public reg< uint32_t, base_addr + 0x38, rw, 0x00000000 >
295  {
296  using FSMCEN = regbits< type, 0, 1 >; /**< Flexible static memory controller module clock enable */
297  };
298 
299  /**
300  * APB1 peripheral clock enable register
301  */
302  struct APB1ENR
303  : public reg< uint32_t, base_addr + 0x40, rw, 0x00000000 >
304  {
305  using DACEN = regbits< type, 29, 1 >; /**< DAC interface clock enable */
306  using PWREN = regbits< type, 28, 1 >; /**< Power interface clock enable */
307  using CAN2EN = regbits< type, 26, 1 >; /**< CAN 2 clock enable */
308  using CAN1EN = regbits< type, 25, 1 >; /**< CAN 1 clock enable */
309  using I2C3EN = regbits< type, 23, 1 >; /**< I2C3 clock enable */
310  using I2C2EN = regbits< type, 22, 1 >; /**< I2C2 clock enable */
311  using I2C1EN = regbits< type, 21, 1 >; /**< I2C1 clock enable */
312  using UART5EN = regbits< type, 20, 1 >; /**< UART5 clock enable */
313  using UART4EN = regbits< type, 19, 1 >; /**< UART4 clock enable */
314  using USART3EN = regbits< type, 18, 1 >; /**< USART3 clock enable */
315  using USART2EN = regbits< type, 17, 1 >; /**< USART 2 clock enable */
316  using SPI3EN = regbits< type, 15, 1 >; /**< SPI3 clock enable */
317  using SPI2EN = regbits< type, 14, 1 >; /**< SPI2 clock enable */
318  using WWDGEN = regbits< type, 11, 1 >; /**< Window watchdog clock enable */
319  using TIM14EN = regbits< type, 8, 1 >; /**< TIM14 clock enable */
320  using TIM13EN = regbits< type, 7, 1 >; /**< TIM13 clock enable */
321  using TIM12EN = regbits< type, 6, 1 >; /**< TIM12 clock enable */
322  using TIM7EN = regbits< type, 5, 1 >; /**< TIM7 clock enable */
323  using TIM6EN = regbits< type, 4, 1 >; /**< TIM6 clock enable */
324  using TIM5EN = regbits< type, 3, 1 >; /**< TIM5 clock enable */
325  using TIM4EN = regbits< type, 2, 1 >; /**< TIM4 clock enable */
326  using TIM3EN = regbits< type, 1, 1 >; /**< TIM3 clock enable */
327  using TIM2EN = regbits< type, 0, 1 >; /**< TIM2 clock enable */
328  };
329 
330  /**
331  * APB2 peripheral clock enable register
332  */
333  struct APB2ENR
334  : public reg< uint32_t, base_addr + 0x44, rw, 0x00000000 >
335  {
336  using TIM11EN = regbits< type, 18, 1 >; /**< TIM11 clock enable */
337  using TIM10EN = regbits< type, 17, 1 >; /**< TIM10 clock enable */
338  using TIM9EN = regbits< type, 16, 1 >; /**< TIM9 clock enable */
339  using SYSCFGEN = regbits< type, 14, 1 >; /**< System configuration controller clock enable */
340  using SPI1EN = regbits< type, 12, 1 >; /**< SPI1 clock enable */
341  using SDIOEN = regbits< type, 11, 1 >; /**< SDIO clock enable */
342  using ADC3EN = regbits< type, 10, 1 >; /**< ADC3 clock enable */
343  using ADC2EN = regbits< type, 9, 1 >; /**< ADC2 clock enable */
344  using ADC1EN = regbits< type, 8, 1 >; /**< ADC1 clock enable */
345  using USART6EN = regbits< type, 5, 1 >; /**< USART6 clock enable */
346  using USART1EN = regbits< type, 4, 1 >; /**< USART1 clock enable */
347  using TIM8EN = regbits< type, 1, 1 >; /**< TIM8 clock enable */
348  using TIM1EN = regbits< type, 0, 1 >; /**< TIM1 clock enable */
349  };
350 
351  /**
352  * AHB1 peripheral clock enable in low power mode register
353  */
354  struct AHB1LPENR
355  : public reg< uint32_t, base_addr + 0x50, rw, 0x7E6791FF >
356  {
357  using OTGHSULPILPEN = regbits< type, 30, 1 >; /**< USB OTG HS ULPI clock enable during sleep mode */
358  using OTGHSLPEN = regbits< type, 29, 1 >; /**< USB OTG HS clock enable during sleep mode */
359  using ETHMACPTPLPEN = regbits< type, 28, 1 >; /**< Ethernet PTP clock enable during sleep mode */
360  using ETHMACRXLPEN = regbits< type, 27, 1 >; /**< Ethernet reception clock enable during sleep mode */
361  using ETHMACTXLPEN = regbits< type, 26, 1 >; /**< Ethernet transmission clock enable during sleep mode */
362  using ETHMACLPEN = regbits< type, 25, 1 >; /**< Ethernet MAC clock enable during sleep mode */
363  using DMA2LPEN = regbits< type, 22, 1 >; /**< DMA2 clock enable during sleep mode */
364  using DMA1LPEN = regbits< type, 21, 1 >; /**< DMA1 clock enable during sleep mode */
365  using BKPSRAMLPEN = regbits< type, 18, 1 >; /**< Backup SRAM interface clock enable during sleep mode */
366  using SRAM2LPEN = regbits< type, 17, 1 >; /**< SRAM 2 interface clock enable during sleep mode */
367  using SRAM1LPEN = regbits< type, 16, 1 >; /**< SRAM 1 interface clock enable during sleep mode */
368  using FLITFLPEN = regbits< type, 15, 1 >; /**< Flash interface clock enable during sleep mode */
369  using CRCLPEN = regbits< type, 12, 1 >; /**< CRC clock enable during sleep mode */
370  using GPIOILPEN = regbits< type, 8, 1 >; /**< IO port I clock enable during sleep mode */
371  using GPIOHLPEN = regbits< type, 7, 1 >; /**< IO port H clock enable during sleep mode */
372  using GPIOGLPEN = regbits< type, 6, 1 >; /**< IO port G clock enable during sleep mode */
373  using GPIOFLPEN = regbits< type, 5, 1 >; /**< IO port F clock enable during sleep mode */
374  using GPIOELPEN = regbits< type, 4, 1 >; /**< IO port E clock enable during sleep mode */
375  using GPIODLPEN = regbits< type, 3, 1 >; /**< IO port D clock enable during sleep mode */
376  using GPIOCLPEN = regbits< type, 2, 1 >; /**< IO port C clock enable during sleep mode */
377  using GPIOBLPEN = regbits< type, 1, 1 >; /**< IO port B clock enable during sleep mode */
378  using GPIOALPEN = regbits< type, 0, 1 >; /**< IO port A clock enable during sleep mode */
379  };
380 
381  /**
382  * AHB2 peripheral clock enable in low power mode register
383  */
384  struct AHB2LPENR
385  : public reg< uint32_t, base_addr + 0x54, rw, 0x000000F1 >
386  {
387  using OTGFSLPEN = regbits< type, 7, 1 >; /**< USB OTG FS clock enable during sleep mode */
388  using RNGLPEN = regbits< type, 6, 1 >; /**< Random number generator clock enable during sleep mode */
389  using DCMILPEN = regbits< type, 0, 1 >; /**< Camera interface enable during sleep mode */
390  };
391 
392  /**
393  * AHB3 peripheral clock enable in low power mode register
394  */
395  struct AHB3LPENR
396  : public reg< uint32_t, base_addr + 0x58, rw, 0x00000001 >
397  {
398  using FSMCLPEN = regbits< type, 0, 1 >; /**< Flexible static memory controller module clock enable during sleep mode */
399  };
400 
401  /**
402  * APB1 peripheral clock enable in low power mode register
403  */
404  struct APB1LPENR
405  : public reg< uint32_t, base_addr + 0x60, rw, 0x36FEC9FF >
406  {
407  using DACLPEN = regbits< type, 29, 1 >; /**< DAC interface clock enable during sleep mode */
408  using PWRLPEN = regbits< type, 28, 1 >; /**< Power interface clock enable during sleep mode */
409  using CAN2LPEN = regbits< type, 26, 1 >; /**< CAN 2 clock enable during sleep mode */
410  using CAN1LPEN = regbits< type, 25, 1 >; /**< CAN 1 clock enable during sleep mode */
411  using I2C3LPEN = regbits< type, 23, 1 >; /**< I2C3 clock enable during sleep mode */
412  using I2C2LPEN = regbits< type, 22, 1 >; /**< I2C2 clock enable during sleep mode */
413  using I2C1LPEN = regbits< type, 21, 1 >; /**< I2C1 clock enable during sleep mode */
414  using UART5LPEN = regbits< type, 20, 1 >; /**< UART5 clock enable during sleep mode */
415  using UART4LPEN = regbits< type, 19, 1 >; /**< UART4 clock enable during sleep mode */
416  using USART3LPEN = regbits< type, 18, 1 >; /**< USART3 clock enable during sleep mode */
417  using USART2LPEN = regbits< type, 17, 1 >; /**< USART2 clock enable during sleep mode */
418  using SPI3LPEN = regbits< type, 15, 1 >; /**< SPI3 clock enable during sleep mode */
419  using SPI2LPEN = regbits< type, 14, 1 >; /**< SPI2 clock enable during sleep mode */
420  using WWDGLPEN = regbits< type, 11, 1 >; /**< Window watchdog clock enable during sleep mode */
421  using TIM14LPEN = regbits< type, 8, 1 >; /**< TIM14 clock enable during sleep mode */
422  using TIM13LPEN = regbits< type, 7, 1 >; /**< TIM13 clock enable during sleep mode */
423  using TIM12LPEN = regbits< type, 6, 1 >; /**< TIM12 clock enable during sleep mode */
424  using TIM7LPEN = regbits< type, 5, 1 >; /**< TIM7 clock enable during sleep mode */
425  using TIM6LPEN = regbits< type, 4, 1 >; /**< TIM6 clock enable during sleep mode */
426  using TIM5LPEN = regbits< type, 3, 1 >; /**< TIM5 clock enable during sleep mode */
427  using TIM4LPEN = regbits< type, 2, 1 >; /**< TIM4 clock enable during sleep mode */
428  using TIM3LPEN = regbits< type, 1, 1 >; /**< TIM3 clock enable during sleep mode */
429  using TIM2LPEN = regbits< type, 0, 1 >; /**< TIM2 clock enable during sleep mode */
430  };
431 
432  /**
433  * APB2 peripheral clock enabled in low power mode register
434  */
435  struct APB2LPENR
436  : public reg< uint32_t, base_addr + 0x64, rw, 0x00075F33 >
437  {
438  using TIM11LPEN = regbits< type, 18, 1 >; /**< TIM11 clock enable during sleep mode */
439  using TIM10LPEN = regbits< type, 17, 1 >; /**< TIM10 clock enable during sleep mode */
440  using TIM9LPEN = regbits< type, 16, 1 >; /**< TIM9 clock enable during sleep mode */
441  using SYSCFGLPEN = regbits< type, 14, 1 >; /**< System configuration controller clock enable during sleep mode */
442  using SPI1LPEN = regbits< type, 12, 1 >; /**< SPI 1 clock enable during sleep mode */
443  using SDIOLPEN = regbits< type, 11, 1 >; /**< SDIO clock enable during sleep mode */
444  using ADC3LPEN = regbits< type, 10, 1 >; /**< ADC 3 clock enable during sleep mode */
445  using ADC2LPEN = regbits< type, 9, 1 >; /**< ADC2 clock enable during sleep mode */
446  using ADC1LPEN = regbits< type, 8, 1 >; /**< ADC1 clock enable during sleep mode */
447  using USART6LPEN = regbits< type, 5, 1 >; /**< USART6 clock enable during sleep mode */
448  using USART1LPEN = regbits< type, 4, 1 >; /**< USART1 clock enable during sleep mode */
449  using TIM8LPEN = regbits< type, 1, 1 >; /**< TIM8 clock enable during sleep mode */
450  using TIM1LPEN = regbits< type, 0, 1 >; /**< TIM1 clock enable during sleep mode */
451  };
452 
453  /**
454  * Backup domain control register
455  */
456  struct BDCR
457  : public reg< uint32_t, base_addr + 0x70, rw, 0x00000000 >
458  {
459  using BDRST = regbits< type, 16, 1 >; /**< Backup domain software reset */
460  using RTCEN = regbits< type, 15, 1 >; /**< RTC clock enable */
461  using RTCSEL1 = regbits< type, 9, 1 >; /**< RTC clock source selection */
462  using RTCSEL0 = regbits< type, 8, 1 >; /**< RTC clock source selection */
463  using LSEBYP = regbits< type, 2, 1 >; /**< External low-speed oscillator bypass */
464  using LSERDY = regbits< type, 1, 1 >; /**< External low-speed oscillator ready */
465  using LSEON = regbits< type, 0, 1 >; /**< External low-speed oscillator enable */
466  };
467 
468  /**
469  * Clock control and status register
470  */
471  struct CSR
472  : public reg< uint32_t, base_addr + 0x74, rw, 0x0E000000 >
473  {
474  using LPWRRSTF = regbits< type, 31, 1 >; /**< Low-power reset flag */
475  using WWDGRSTF = regbits< type, 30, 1 >; /**< Window watchdog reset flag */
476  using WDGRSTF = regbits< type, 29, 1 >; /**< Independent watchdog reset flag */
477  using SFTRSTF = regbits< type, 28, 1 >; /**< Software reset flag */
478  using PORRSTF = regbits< type, 27, 1 >; /**< POR/PDR reset flag */
479  using PADRSTF = regbits< type, 26, 1 >; /**< PIN reset flag */
480  using BORRSTF = regbits< type, 25, 1 >; /**< BOR reset flag */
481  using RMVF = regbits< type, 24, 1 >; /**< Remove reset flag */
482  using LSIRDY = regbits< type, 1, 1 >; /**< Internal low-speed oscillator ready */
483  using LSION = regbits< type, 0, 1 >; /**< Internal low-speed oscillator enable */
484  };
485 
486  /**
487  * Spread spectrum clock generation register
488  */
489  struct SSCGR
490  : public reg< uint32_t, base_addr + 0x80, rw, 0x00000000 >
491  {
492  using SSCGEN = regbits< type, 31, 1 >; /**< Spread spectrum modulation enable */
493  using SPREADSEL = regbits< type, 30, 1 >; /**< Spread Select */
494  using INCSTEP = regbits< type, 13, 15 >; /**< Incrementation step */
495  using MODPER = regbits< type, 0, 13 >; /**< Modulation period */
496  };
497 
498  /**
499  * PLLI2S configuration register
500  */
501  struct PLLI2SCFGR
502  : public reg< uint32_t, base_addr + 0x84, rw, 0x20003000 >
503  {
504  using PLLI2SR = regbits< type, 28, 3 >; /**< PLLI2S division factor for I2S clocks */
505  using PLLI2SN = regbits< type, 6, 9 >; /**< PLLI2S multiplication factor for VCO */
506  };
507 };
508 } // namespace mptl
509 
510 
511 #endif // ARCH_REG_RCC_HPP_INCLUDED
mptl::RCC::CFGR
Clock configuration register.
Definition: rcc.hpp:78
mptl::RCC::SSCGR
Spread spectrum clock generation register.
Definition: rcc.hpp:489
mptl::RCC::AHB2ENR
AHB2 peripheral clock enable register.
Definition: rcc.hpp:282
mptl::RCC::base_addr
static constexpr reg_addr_t base_addr
Definition: rcc.hpp:40
mptl::RCC::APB2ENR
APB2 peripheral clock enable register.
Definition: rcc.hpp:333
mptl::RCC::PLLI2SCFGR
PLLI2S configuration register.
Definition: rcc.hpp:501
mptl::reg_addr_t
uintptr_t reg_addr_t
mptl::RCC::CFGR::__SWx
System clock Switch.
Definition: rcc.hpp:111
mptl::RCC::BDCR
Backup domain control register.
Definition: rcc.hpp:456
mptl::RCC::AHB1RSTR
AHB1 peripheral reset register.
Definition: rcc.hpp:163
mptl::RCC::AHB2RSTR
AHB2 peripheral reset register.
Definition: rcc.hpp:185
mptl::RCC::AHB3RSTR
AHB3 peripheral reset register.
Definition: rcc.hpp:196
mptl::RCC::CSR
Clock control and status register.
Definition: rcc.hpp:471
mptl::RCC::CIR
Clock interrupt register.
Definition: rcc.hpp:135
mptl::RCC::AHB2LPENR
AHB2 peripheral clock enable in low power mode register.
Definition: rcc.hpp:384
mptl::RCC::CR
Clock control register.
Definition: rcc.hpp:45
mptl::RCC::AHB1LPENR
AHB1 peripheral clock enable in low power mode register.
Definition: rcc.hpp:354
mptl::RCC::APB1RSTR
APB1 peripheral reset register.
Definition: rcc.hpp:205
mptl::RCC::APB2RSTR
APB2 peripheral reset register.
Definition: rcc.hpp:236
mptl::RCC::CFGR::__PPREx
APB1/2 prescaler.
Definition: rcc.hpp:83
mptl::RCC::CFGR::__HPRE
AHB prescaler.
Definition: rcc.hpp:95
mptl::RCC::AHB1ENR
AHB1 peripheral clock register.
Definition: rcc.hpp:255
mptl::RCC::APB1ENR
APB1 peripheral clock enable register.
Definition: rcc.hpp:302
mptl::RCC::APB2LPENR
APB2 peripheral clock enabled in low power mode register.
Definition: rcc.hpp:435
mptl::RCC::PLLCFGR
PLL configuration register.
Definition: rcc.hpp:65
mptl::RCC::APB1LPENR
APB1 peripheral clock enable in low power mode register.
Definition: rcc.hpp:404
mptl::RCC
Reset and clock control.
Definition: rcc.hpp:38
mptl::RCC::AHB3LPENR
AHB3 peripheral clock enable in low power mode register.
Definition: rcc.hpp:395
mptl::RCC::AHB3ENR
AHB3 peripheral clock enable register.
Definition: rcc.hpp:293
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