Class Hierarchy

This inheritance list is sorted roughly, but not completely, alphabetically:

[detail level 1234]

Cmptl::sane_typelist::_typelist_append< class, U > [external]
Cmptl::typelist_element::_typelist_append< class, Tp > [external]
Cmptl::sane_typelist::all_derived_from< class > [external]
Cmptl::reglist::all_reg_type< Treg > [external]
Cmptl::sane_typelist::all_true [external]
Cmptl::arm_cortex_vector_table< vt_size > [external]
Cmptl::bitband_periph [external]
Cmptl::usart_stm32_common< _usart_no, system_clock_type >::clock_phase
Cmptl::spi_stm32_common< _spi_no, system_clock_type >::clock_phase
Cmptl::usart_stm32_common< _usart_no, system_clock_type >::clock_polarity
Cmptl::spi_stm32_common< _spi_no, system_clock_type >::clock_polarity
Cmptl::sane_typelist::contains< class > [external]
Cmptl::sane_typelist::contains_derived_from< class > [external]
Cmptl::systick_clock::core< class, _freq > [external]
Cmptl::core_base [external]
►CCR2
Cmptl::SPI_Common_Ext< base_addr >::CR2
Cmptl::cycle_counter [external]
Cmptl::spi_stm32_common< _spi_no, system_clock_type >::data_direction
Cmptl::DEBUG [external]
Cmptl::dwt [external]
Cmptl::DWT [external]
Cmptl::systick_clock::external< class, _freq > [external]
►Cmptl::fifo< class > [external]
►Cmptl::ring_buffer< class, size > [external]
Cmptl::counted_ring_buffer< class, size > [external]
Cmptl::sane_typelist::filter_is_base_of< class > [external]
Cmptl::usart_stm32_common< _usart_no, system_clock_type >::flow_control
Cmptl::spi_stm32_common< _spi_no, system_clock_type >::frame_format
Cmptl::gpio_analog_io_base< class > [external]
Cmptl::gpio_input_base< class, active_state > [external]
Cmptl::gpio_led_base< class > [external]
Cmptl::gpio_output_base< class, active_state > [external]
Cmptl::irq_base< _irqn > [external]
►Cirq_base< irqn > [external]
Cmptl::core_exception< irqn > [external]
Cmptl::irq_channel< irqn > [external]
Cmptl::reg::merge< class, Rm > [external]
Cmptl::regmask::merge< class > [external]
Cmptl::MPU [external]
Cmptl::NVIC [external]
Cmptl::sane_typelist::pack< class > [external]
Cmptl::usart_stm32_common< _usart_no, system_clock_type >::parity
►CRb
Cmptl::SPI_Common< _base_addr >::CR1::__BR< Rb >	Baud Rate Control
Cmptl::reg_access< Tp, _addr, _permission, reset_value > [external]
►Cmptl::reg_access< Tp, 0xE000E010, rw, _reset_value > [external]
►Cmptl::reg< uint32_t, 0xE000E010, rw > [external]
Cmptl::SCB::STCSR [external]
►Cmptl::reg_access< Tp, 0xE000E014, rw, _reset_value > [external]
►Cmptl::reg< uint32_t, 0xE000E014, rw > [external]
Cmptl::SCB::STRVR [external]
►Cmptl::reg_access< Tp, 0xE000E018, rw, _reset_value > [external]
►Cmptl::reg< uint32_t, 0xE000E018, rw > [external]
Cmptl::SCB::STCVR [external]
►Cmptl::reg_access< Tp, 0xE000E01C, ro, _reset_value > [external]
►Cmptl::reg< uint32_t, 0xE000E01C, ro > [external]
Cmptl::SCB::STCR [external]
►Cmptl::reg_access< Tp, 0xE000E100+4 *reg_index, rw, _reset_value > [external]
►Cmptl::reg< uint32_t, 0xE000E100+4 *reg_index, rw > [external]
Cmptl::NVIC::ISER< reg_index > [external]
►Cmptl::reg_access< Tp, 0xE000E180+4 *reg_index, rw, _reset_value > [external]
►Cmptl::reg< uint32_t, 0xE000E180+4 *reg_index, rw > [external]
Cmptl::NVIC::ICER< reg_index > [external]
►Cmptl::reg_access< Tp, 0xE000E200+4 *reg_index, rw, _reset_value > [external]
►Cmptl::reg< uint32_t, 0xE000E200+4 *reg_index, rw > [external]
Cmptl::NVIC::ISPR< reg_index > [external]
►Cmptl::reg_access< Tp, 0xE000E280+4 *reg_index, rw, _reset_value > [external]
►Cmptl::reg< uint32_t, 0xE000E280+4 *reg_index, rw > [external]
Cmptl::NVIC::ICPR< reg_index > [external]
►Cmptl::reg_access< Tp, 0xE000E300+4 *reg_index, ro, _reset_value > [external]
►Cmptl::reg< uint32_t, 0xE000E300+4 *reg_index, ro > [external]
Cmptl::NVIC::IABR< reg_index > [external]
►Cmptl::reg_access< Tp, 0xE000E400+4 *reg_index, rw, _reset_value > [external]
►Cmptl::reg< uint32_t, 0xE000E400+4 *reg_index, rw > [external]
Cmptl::NVIC::IPR< reg_index > [external]
►Cmptl::reg_access< Tp, 0xE000ED00, ro, _reset_value > [external]
►Cmptl::reg< uint32_t, 0xE000ED00, ro > [external]
Cmptl::SCB::CPUID [external]
►Cmptl::reg_access< Tp, 0xE000ED04, rw, _reset_value > [external]
►Cmptl::reg< uint32_t, 0xE000ED04, rw > [external]
Cmptl::SCB::ICSR [external]
►Cmptl::reg_access< Tp, 0xE000ED08, rw, _reset_value > [external]
►Cmptl::reg< uint32_t, 0xE000ED08, rw > [external]
Cmptl::SCB::VTOR [external]
►Cmptl::reg_access< Tp, 0xE000ED0C, rw, _reset_value > [external]
►Cmptl::reg< uint32_t, 0xE000ED0C, rw > [external]
Cmptl::SCB::AIRCR [external]
►Cmptl::reg_access< Tp, 0xE000ED10, rw, _reset_value > [external]
►Cmptl::reg< uint32_t, 0xE000ED10, rw > [external]
Cmptl::SCB::SCR [external]
►Cmptl::reg_access< Tp, 0xE000ED14, rw, 0x00000200 > [external]
►Cmptl::reg< uint32_t, 0xE000ED14, rw, 0x00000200 > [external]
Cmptl::SCB::CCR [external]
►Cmptl::reg_access< Tp, 0xE000ED18+4 *reg_index, rw, _reset_value > [external]
►Cmptl::reg< uint32_t, 0xE000ED18+4 *reg_index, rw > [external]
Cmptl::SCB::SHPR< reg_index > [external]
►Cmptl::reg_access< Tp, 0xE000ED24, rw, _reset_value > [external]
►Cmptl::reg< uint32_t, 0xE000ED24, rw > [external]
Cmptl::SCB::SHCSR [external]
►Cmptl::reg_access< Tp, 0xE000ED28, rw, _reset_value > [external]
►Cmptl::reg< uint32_t, 0xE000ED28, rw > [external]
Cmptl::SCB::CFSR [external]
►Cmptl::reg_access< Tp, 0xE000ED2C, rw, _reset_value > [external]
►Cmptl::reg< uint32_t, 0xE000ED2C, rw > [external]
Cmptl::SCB::HFSR [external]
►Cmptl::reg_access< Tp, 0xE000ED30, rw, _reset_value > [external]
►Cmptl::reg< uint32_t, 0xE000ED30, rw > [external]
Cmptl::SCB::DFSR [external]
►Cmptl::reg_access< Tp, 0xE000EDFC, rw, _reset_value > [external]
►Cmptl::reg< uint32_t, 0xE000EDFC, rw > [external]
Cmptl::DEBUG::DEMCR [external]
►Creg_access< Tp, addr, permission, _reset_value > [external]
Cmptl::reg< class, addr, permission, _reset_value > [external]
►Cmptl::reg_access< Tp, base_addr+0x0, rw, 0x0000 > [external]
►Cmptl::reg< std::uint_fast16_t, base_addr+0x0, rw, 0x0000 > [external]
Cmptl::TIM_common< _base_addr >::CR1	Control register 1
►Cmptl::reg_access< Tp, base_addr+0x00, rw, 0x0000 > [external]
►Cmptl::reg< std::uint_fast16_t, base_addr+0x00, rw, 0x0000 > [external]
Cmptl::SPI_Common< _base_addr >::CR1	Control register 1
►Cmptl::reg_access< Tp, base_addr+0x00, rw, 0x00c0 > [external]
►Cmptl::reg< std::uint_fast16_t, base_addr+0x00, rw, 0x00c0 > [external]
Cmptl::USART_common< base_addr >::SR	Status register
►Cmptl::reg_access< Tp, base_addr+0x04, rw, 0x0000 > [external]
►Cmptl::reg< std::uint_fast16_t, base_addr+0x04, rw, 0x0000 > [external]
Cmptl::SPI_Common< _base_addr >::CR2	Control register 2
►Cmptl::reg_access< Tp, base_addr+0x04, rw, 0x00000000 > [external]
►Cmptl::reg< std::uint_fast16_t, base_addr+0x04, rw, 0x00000000 > [external]
Cmptl::USART_common< base_addr >::DR	Data register
►Cmptl::reg_access< Tp, base_addr+0x08, rw, 0x0000 > [external]
►Cmptl::reg< std::uint_fast16_t, base_addr+0x08, rw, 0x0000 > [external]
Cmptl::USART_common< base_addr >::BRR	Baud rate register
►Cmptl::reg_access< Tp, base_addr+0x08, rw, 0x0002 > [external]
►Cmptl::reg< std::uint_fast16_t, base_addr+0x08, rw, 0x0002 > [external]
Cmptl::SPI_Common< _base_addr >::SR	Status register
►Cmptl::reg_access< Tp, base_addr+0x0c, rw, 0x0000 > [external]
►Cmptl::reg< std::uint_fast16_t, base_addr+0x0c, rw, 0x0000 > [external]
►Cmptl::USART_common< base_addr >::CR1	Control register 1
Cmptl::USART_common_ext< base_addr >::CR1
►Cmptl::reg_access< Tp, base_addr+0x10, rw, 0x0000 > [external]
►Cmptl::reg< std::uint_fast16_t, base_addr+0x10, rw, 0x0000 > [external]
Cmptl::TIM_common< _base_addr >::SR	Status register
Cmptl::USART_common< base_addr >::CR2	Control register 2
►Cmptl::reg_access< Tp, base_addr+0x14, rw, 0x0000 > [external]
►Cmptl::reg< std::uint_fast16_t, base_addr+0x14, rw, 0x0000 > [external]
►Cmptl::USART_common< base_addr >::CR3	Control register 3
Cmptl::USART_common_ext< base_addr >::CR3
►Cmptl::reg_access< Tp, base_addr+0x14, wo, 0x0000 > [external]
►Cmptl::reg< std::uint_fast16_t, base_addr+0x14, wo, 0x0000 > [external]
Cmptl::TIM_common< _base_addr >::EGR	Event generation register
►Cmptl::reg_access< Tp, base_addr+0x18, rw, 0x0000 > [external]
►Cmptl::reg< std::uint_fast16_t, base_addr+0x18, rw, 0x0000 > [external]
Cmptl::TIM_common< _base_addr >::CCMR1_Input	Capture/compare mode register 1 (input mode)
Cmptl::TIM_common< _base_addr >::CCMR1_Output	Capture/compare mode register 1 (output mode)
Cmptl::USART_common< base_addr >::GTPR	Guard time and prescaler register
►Cmptl::reg_access< Tp, base_addr+0x1c, rw, 0x0000 > [external]
►Cmptl::reg< std::uint_fast16_t, base_addr+0x1c, rw, 0x0000 > [external]
Cmptl::SPI_Common< _base_addr >::I2SCFGR	I2S configuration register
Cmptl::TIM_common< _base_addr >::CCMR2_Input	Capture/compare mode register 2 (input mode)
Cmptl::TIM_common< _base_addr >::CCMR2_Output	Capture/compare mode register 2 (output mode)
►Cmptl::reg_access< Tp, base_addr+0x20, rw, 00000010 > [external]
►Cmptl::reg< std::uint_fast16_t, base_addr+0x20, rw, 00000010 > [external]
Cmptl::SPI_Common< _base_addr >::I2SPR	I2S prescaler register
►Cmptl::reg_access< Tp, base_addr+0x20, rw, 0x0000 > [external]
►Cmptl::reg< std::uint_fast16_t, base_addr+0x20, rw, 0x0000 > [external]
Cmptl::TIM_common< _base_addr >::CCER	Capture/compare enable register
►Cmptl::reg_access< Tp, base_addr+0x30, rw, 0x0000 > [external]
►Cmptl::reg< std::uint_fast16_t, base_addr+0x30, rw, 0x0000 > [external]
Cmptl::TIM_common< _base_addr >::RCR	Repetition counter register
►Cmptl::reg_access< Tp, base_addr+0x4, rw, 0x0000 > [external]
►Cmptl::reg< std::uint_fast16_t, base_addr+0x4, rw, 0x0000 > [external]
Cmptl::TIM_common< _base_addr >::CR2	Control register 2
►Cmptl::reg_access< Tp, base_addr+0x44, rw, 0x0000 > [external]
►Cmptl::reg< std::uint_fast16_t, base_addr+0x44, rw, 0x0000 > [external]
Cmptl::TIM_common< _base_addr >::BDTR	Break and dead-time register
►Cmptl::reg_access< Tp, base_addr+0x48, rw, 0x0000 > [external]
►Cmptl::reg< std::uint_fast16_t, base_addr+0x48, rw, 0x0000 > [external]
Cmptl::TIM_common< _base_addr >::DCR	DMA control register
►Cmptl::reg_access< Tp, base_addr+0x8, rw, 0x0000 > [external]
►Cmptl::reg< std::uint_fast16_t, base_addr+0x8, rw, 0x0000 > [external]
Cmptl::TIM_common< _base_addr >::SMCR	Slave mode control register
►Cmptl::reg_access< Tp, base_addr+0xc, rw, 0x0000 > [external]
►Cmptl::reg< std::uint_fast16_t, base_addr+0xc, rw, 0x0000 > [external]
Cmptl::TIM_common< _base_addr >::DIER	DMA/Interrupt enable register
Cmptl::sim::reg_dumper< class, addr > [external]
Cmptl::sim::reg_reaction [external]
Cmptl::reglist< Tp > [external]
Cmptl::sane_typelist< Tp > [external]
Cmptl::SCB [external]
Cmptl::SPI_Common< _base_addr >	Serial peripheral interface (SPI)
►Cmptl::SPI_Common< base_addr >
Cmptl::SPI_Common_Ext< base_addr >	Some architectures (e.g
Cmptl::spi_stm32_common< _spi_no, system_clock_type >
►CSR
Cmptl::SPI_Common_Ext< base_addr >::SR
Cmptl::systick< class > [external]
Cmptl::systick_clock [external]
Cmptl::TIM_common< _base_addr >	Advanced timer
►Cmptl::typelist_element [external]
Cmptl::reg< class, addr, permission, _reset_value > [external]
Cmptl::regmask< Tp, _set_mask, _clear_mask > [external]
Cmptl::typelist_unique_element< unique_type > [external]
Cmptl::reg< std::uint_fast16_t, base_addr+0x0, rw, 0x0000 > [external]
Cmptl::reg< std::uint_fast16_t, base_addr+0x00, rw, 0x0000 > [external]
Cmptl::reg< std::uint_fast16_t, base_addr+0x00, rw, 0x00c0 > [external]
Cmptl::reg< std::uint_fast16_t, base_addr+0x04, rw, 0x0000 > [external]
Cmptl::reg< std::uint_fast16_t, base_addr+0x04, rw, 0x00000000 > [external]
Cmptl::reg< std::uint_fast16_t, base_addr+0x08, rw, 0x0000 > [external]
Cmptl::reg< std::uint_fast16_t, base_addr+0x08, rw, 0x0002 > [external]
Cmptl::reg< std::uint_fast16_t, base_addr+0x0c, rw, 0x0000 > [external]
Cmptl::reg< std::uint_fast16_t, base_addr+0x10, rw, 0x0000 > [external]
Cmptl::reg< std::uint_fast16_t, base_addr+0x14, rw, 0x0000 > [external]
Cmptl::reg< std::uint_fast16_t, base_addr+0x14, wo, 0x0000 > [external]
Cmptl::reg< std::uint_fast16_t, base_addr+0x18, rw, 0x0000 > [external]
Cmptl::reg< std::uint_fast16_t, base_addr+0x1c, rw, 0x0000 > [external]
Cmptl::reg< std::uint_fast16_t, base_addr+0x20, rw, 00000010 > [external]
Cmptl::reg< std::uint_fast16_t, base_addr+0x20, rw, 0x0000 > [external]
Cmptl::reg< std::uint_fast16_t, base_addr+0x30, rw, 0x0000 > [external]
Cmptl::reg< std::uint_fast16_t, base_addr+0x4, rw, 0x0000 > [external]
Cmptl::reg< std::uint_fast16_t, base_addr+0x44, rw, 0x0000 > [external]
Cmptl::reg< std::uint_fast16_t, base_addr+0x48, rw, 0x0000 > [external]
Cmptl::reg< std::uint_fast16_t, base_addr+0x8, rw, 0x0000 > [external]
Cmptl::reg< std::uint_fast16_t, base_addr+0xc, rw, 0x0000 > [external]
Cmptl::reg< uint32_t, 0xE000E010, rw > [external]
Cmptl::reg< uint32_t, 0xE000E014, rw > [external]
Cmptl::reg< uint32_t, 0xE000E018, rw > [external]
Cmptl::reg< uint32_t, 0xE000E01C, ro > [external]
Cmptl::reg< uint32_t, 0xE000E100+4 *reg_index, rw > [external]
Cmptl::reg< uint32_t, 0xE000E180+4 *reg_index, rw > [external]
Cmptl::reg< uint32_t, 0xE000E200+4 *reg_index, rw > [external]
Cmptl::reg< uint32_t, 0xE000E280+4 *reg_index, rw > [external]
Cmptl::reg< uint32_t, 0xE000E300+4 *reg_index, ro > [external]
Cmptl::reg< uint32_t, 0xE000E400+4 *reg_index, rw > [external]
Cmptl::reg< uint32_t, 0xE000ED00, ro > [external]
Cmptl::reg< uint32_t, 0xE000ED04, rw > [external]
Cmptl::reg< uint32_t, 0xE000ED08, rw > [external]
Cmptl::reg< uint32_t, 0xE000ED0C, rw > [external]
Cmptl::reg< uint32_t, 0xE000ED10, rw > [external]
Cmptl::reg< uint32_t, 0xE000ED14, rw, 0x00000200 > [external]
Cmptl::reg< uint32_t, 0xE000ED18+4 *reg_index, rw > [external]
Cmptl::reg< uint32_t, 0xE000ED24, rw > [external]
Cmptl::reg< uint32_t, 0xE000ED28, rw > [external]
Cmptl::reg< uint32_t, 0xE000ED2C, rw > [external]
Cmptl::reg< uint32_t, 0xE000ED30, rw > [external]
Cmptl::reg< uint32_t, 0xE000EDFC, rw > [external]
►Cregmask< reg_type,((1ul<< width) - 1)<< offset,((1ul<< width) - 1)<< offset > [external]
►Cregbits< reg_type, offset+bit_no, 1 > [external]
Cmptl::regbits::bit< bit_no > [external]
►Cregmask< Tp,((1ul<< width) - 1)<< offset,((1ul<< width) - 1)<< offset > [external]
Cmptl::regbits< Tp, offset, width > [external]
►Cregmask< Tp::reg_type, Tp::value_from(_value), Tp::clear_mask > [external]
Cmptl::regval< class, _value > [external]
►Cmptl::regmask< Tp::reg_type, Tp::value_from(prescaler), Tp::clear_mask > [external]
►Cmptl::regval< Rb, prescaler==2 ? 0x0 :prescaler==4 ? 0x1 :prescaler==8 ? 0x2 :prescaler==16 ? 0x3 :prescaler==32 ? 0x4 :prescaler==64 ? 0x5 :prescaler==128 ? 0x6 :prescaler==256 ? 0x7 :0 > [external]
Cmptl::SPI_Common< _base_addr >::CR1::__BR< Rb >::Prescaler< prescaler >
►Ctypelist_unique_element< irq_handler_base > [external]
►Cmptl::irq_handler_base [external]
Cmptl::irq_handler< class, isr > [external]
Cmptl::sane_typelist< Tp >::unique_element [external]
►Cmptl::USART_common< base_addr >	Universal synchronous asynchronous receiver transmitter (USART), common to all stm32 processors
Cmptl::USART_common_ext< base_addr >	Some architectures (e.g
Cmptl::usart_irq_stream< usart_type, _fifo_type, _crlf, debug_irqs >
Cmptl::usart_stm32_common< _usart_no, system_clock_type >
Cmptl::vector_table< stack_top, class, default_isr > [external]