OpenMPTL - STM32F4
C++ Microprocessor Template Library
flash.hpp
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1 /*
2  * OpenMPTL - C++ Microprocessor Template Library
3  *
4  * Copyright (C) 2012-2017 Axel Burri <axel@tty0.ch>
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License as published by
8  * the Free Software Foundation; either version 3 of the License, or
9  * (at your option) any later version.
10  *
11  * This program is distributed in the hope that it will be useful,
12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14  * GNU General Public License for more details.
15  *
16  * You should have received a copy of the GNU General Public License
17  * along with this program. If not, see <http://www.gnu.org/licenses/>.
18  *
19  */
20 
21 /*
22  * This program contains derivative representations of CMSIS System
23  * View Description (SVD) files, and is subject to the "End User
24  * License Agreement for STMicroelectronics" (see "STM_License.html"
25  * in the containing directory).
26  */
27 
28 #ifndef ARCH_REG_FLASH_HPP_INCLUDED
29 #define ARCH_REG_FLASH_HPP_INCLUDED
30 
31 #include <register.hpp>
32 
33 namespace mptl {
34 
35 /**
36  * FLASH
37  */
38 struct FLASH
39 {
40  static constexpr reg_addr_t base_addr = 0x40023C00;
41 
42  /**
43  * Flash access control register
44  */
45  struct ACR
46  : public reg< uint32_t, base_addr + 0x00, rw, 0x00000000 >
47  {
48  using DCRST = regbits< type, 12, 1 >; /**< Data cache reset */
49  using ICRST = regbits< type, 11, 1 >; /**< Instruction cache reset */
50  using DCEN = regbits< type, 10, 1 >; /**< Data cache enable */
51  using ICEN = regbits< type, 9, 1 >; /**< Instruction cache enable */
52  using PRFTEN = regbits< type, 8, 1 >; /**< Prefetch enable */
53  using LATENCY = regbits< type, 0, 3 >; /**< Latency */
54  };
55 
56  /**
57  * Flash key register
58  */
60 
61  /**
62  * Flash option key register
63  */
65 
66  /**
67  * Status register
68  */
69  struct SR
70  : public reg< uint32_t, base_addr + 0x0C, rw, 0x00000000 >
71  {
72  using BSY = regbits< type, 16, 1 >; /**< Busy */
73  using PGSERR = regbits< type, 7, 1 >; /**< Programming sequence error */
74  using PGPERR = regbits< type, 6, 1 >; /**< Programming parallelism error */
75  using PGAERR = regbits< type, 5, 1 >; /**< Programming alignment error */
76  using WRPERR = regbits< type, 4, 1 >; /**< Write protection error */
77  using OPERR = regbits< type, 1, 1 >; /**< Operation error */
78  using EOP = regbits< type, 0, 1 >; /**< End of operation */
79  };
80 
81  /**
82  * Control register
83  */
84  struct CR
85  : public reg< uint32_t, base_addr + 0x10, rw, 0x80000000 >
86  {
87  using LOCK = regbits< type, 31, 1 >; /**< Lock */
88  using ERRIE = regbits< type, 25, 1 >; /**< Error interrupt enable */
89  using EOPIE = regbits< type, 24, 1 >; /**< End of operation interrupt enable */
90  using STRT = regbits< type, 16, 1 >; /**< Start */
91  using PSIZE = regbits< type, 8, 2 >; /**< Program size */
92  using SNB = regbits< type, 3, 4 >; /**< Sector number */
93  using MER = regbits< type, 2, 1 >; /**< Mass erase */
94  using SER = regbits< type, 1, 1 >; /**< Sector erase */
95  using PG = regbits< type, 0, 1 >; /**< Programming */
96  };
97 
98  /**
99  * Flash option control register
100  */
101  struct OPTCR
102  : public reg< uint32_t, base_addr + 0x14, rw, 0x00000014 >
103  {
104  /** User option bytes */
105  template<typename Rb>
106  struct __USER
107  : public Rb
108  {
112  };
113 
114  using NWRP = regbits< type, 16, 12 >; /**< Not write protect */
115  using RDP = regbits< type, 8, 8 >; /**< Read protect */
116  using USER = __USER < regbits< type, 5, 3 > >; /**< User option bytes */
117  using BOR_LEV = regbits< type, 2, 2 >; /**< BOR reset Level */
118  using OPTSTRT = regbits< type, 1, 1 >; /**< Option start */
119  using OPTLOCK = regbits< type, 0, 1 >; /**< Option lock */
120  };
121 };
122 
123 } // namespace mptl
124 
125 #endif // ARCH_REG_FLASH_HPP_INCLUDED
Flash option control register.
Definition: flash.hpp:101
uintptr_t reg_addr_t
FLASH.
Definition: flash.hpp:38
static constexpr reg_addr_t base_addr
Definition: flash.hpp:40
User option bytes.
Definition: flash.hpp:106
Control register.
Definition: flash.hpp:84
Status register.
Definition: flash.hpp:69
Flash access control register.
Definition: flash.hpp:45