- f -

• FE : mptl::USART_common< base_addr >::SR
• fifo_type : mptl::usart_irq_stream< usart_type, _fifo_type, _crlf, debug_irqs >
• first_edge : mptl::spi_stm32_common< _spi_no, system_clock_type >::clock_phase , mptl::usart_stm32_common< _usart_no, system_clock_type >::clock_phase
• FRF : mptl::SPI_Common_Ext< base_addr >::CR2