Class List

Here are the classes, structs, unions and interfaces with brief descriptions:

[detail level 123]

▼Nmptl
Carm_cortex_vector_table
Cbitband_periph
Ccore_base
Ccore_exception
Ccounted_ring_buffer [external]
Ccycle_counter	Cycle counter: Count processor clock cycles
▼CDEBUG	Debug Register
CDEMCR	Debug Exception and Monitor Control Register
Cdwt
CDWT	DWT Register
Cfifo [external]
Cgpio_analog_io_base [external]
Cgpio_input_base [external]
Cgpio_led_base [external]
Cgpio_output_base [external]
Cirq_base
Cirq_channel
Cirq_handler [external]
Cirq_handler_base [external]
CMPU	MPU (Memory Protection Unit) Register
▼CNVIC	NVIC (Nested Vectored Interrupt Controller) Register
CIABR	Interrupt Active Bit Register
CICER	Interrupt Set-Enable Registers
CICPR	Interrupt Clear-Pending Registers
CIPR	Interrupt Priority Register
CISER	Interrupt Set-Enable Registers
CISPR	Interrupt Set-Pending Registers
Creg [external]
Creg_access [external]
Cregbits [external]
Creglist [external]
Cregmask [external]
Cregval [external]
Cring_buffer [external]
Csane_typelist [external]
▼CSCB	System Control Register
CAIRCR	Application Interrupt and Reset Control Register
CCCR	Configuration and Control Register
CCFSR	Configurable Fault Status Registers
CCPUID	CPUID Base Register, CPUID
CDFSR	Debug Fault Status Register
CHFSR	HardFault Status Register
CICSR	Interrupt Control and State Register
CSCR	System Control Register
CSHCSR	System Handler Control and State Register
CSHPR	System Handler Priority Register
CSTCR	SysTick Calilbration Value Register
CSTCSR	SysTick Control and Status Register
CSTCVR	SysTick Current Value Register
CSTRVR	SysTick Reload Value Register
CVTOR	Vector Table Offset Register
Csystick
▼Csystick_clock
Ccore	Select core clock (HCLK) as systick clock source
Cexternal	Select external clock (HCLK_DIV8) as systick clock source
Ctypelist_element [external]
Ctypelist_unique_element [external]
Cvector_table	Provides a static vector table (value[], see vector_table_impl above), to be initialized in section ".isr_vector"
Creg_access< Tp, addr, permission, _reset_value > [external]
Cregbits< reg_type, offset+bit_no, 1 > [external]
Cregmask< reg_type,((1ul<< width) - 1)<< offset,((1ul<< width) - 1)<< offset > [external]
Cregmask< Tp,((1ul<< width) - 1)<< offset,((1ul<< width) - 1)<< offset > [external]
Cregmask< Tp::reg_type, Tp::value_from(_value), Tp::clear_mask > [external]
Ctypelist_unique_element< irq_handler_base > [external]